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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
7  */
8 #ifndef __ASM_SN_INTR_H
9 #define __ASM_SN_INTR_H
10 
11 /* Number of interrupt levels associated with each interrupt register. */
12 #define N_INTPEND_BITS		64
13 
14 #define INT_PEND0_BASELVL	0
15 #define INT_PEND1_BASELVL	64
16 
17 #define N_INTPENDJUNK_BITS	8
18 #define INTPENDJUNK_CLRBIT	0x80
19 
20 /*
21  * Macros to manipulate the interrupt register on the calling hub chip.
22  */
23 
24 #define LOCAL_HUB_SEND_INTR(level)				\
25 	LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
26 #define REMOTE_HUB_SEND_INTR(hub, level)			\
27 	REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
28 
29 /*
30  * When clearing the interrupt, make sure this clear does make it
31  * to the hub. Otherwise we could end up losing interrupts.
32  * We do an uncached load of the int_pend0 register to ensure this.
33  */
34 
35 #define LOCAL_HUB_CLR_INTR(level)				\
36 do {								\
37 	LOCAL_HUB_S(PI_INT_PEND_MOD, (level));			\
38 	LOCAL_HUB_L(PI_INT_PEND0);				\
39 } while (0);
40 
41 #define REMOTE_HUB_CLR_INTR(hub, level)				\
42 do {								\
43 	nasid_t	 __hub = (hub);					\
44 								\
45 	REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));		\
46 	REMOTE_HUB_L(__hub, PI_INT_PEND0);			\
47 } while (0);
48 
49 /*
50  * Hard-coded interrupt levels:
51  */
52 
53 /*
54  *	L0 = SW1
55  *	L1 = SW2
56  *	L2 = INT_PEND0
57  *	L3 = INT_PEND1
58  *	L4 = RTC
59  *	L5 = Profiling Timer
60  *	L6 = Hub Errors
61  *	L7 = Count/Compare (T5 counters)
62  */
63 
64 
65 /*
66  * INT_PEND0 hard-coded bits.
67  */
68 
69 /*
70  * INT_PEND0 bits determined by hardware:
71  */
72 #define RESERVED_INTR		 0	/* What is this bit? */
73 #define GFX_INTR_A		 1
74 #define GFX_INTR_B		 2
75 #define PG_MIG_INTR		 3
76 #define UART_INTR		 4
77 #define CC_PEND_A		 5
78 #define CC_PEND_B		 6
79 
80 /*
81  * INT_PEND0 used by the kernel for itself ...
82  */
83 #define CPU_RESCHED_A_IRQ	 7
84 #define CPU_RESCHED_B_IRQ	 8
85 #define CPU_CALL_A_IRQ		 9
86 #define CPU_CALL_B_IRQ		10
87 #define MSC_MESG_INTR		11
88 #define BASE_PCI_IRQ		12
89 
90 /*
91  * INT_PEND0 again, bits determined by hardware / hardcoded:
92  */
93 #define SDISK_INTR		63	/* SABLE name */
94 #define IP_PEND0_6_63		63	/* What is this bit? */
95 
96 /*
97  * INT_PEND1 hard-coded bits:
98  */
99 #define NI_BRDCAST_ERR_A	39
100 #define NI_BRDCAST_ERR_B	40
101 
102 #define LLP_PFAIL_INTR_A	41	/* see ml/SN/SN0/sysctlr.c */
103 #define LLP_PFAIL_INTR_B	42
104 
105 #define TLB_INTR_A		43	/* used for tlb flush random */
106 #define TLB_INTR_B		44
107 
108 #define IP27_INTR_0		45	/* Reserved for PROM use */
109 #define IP27_INTR_1		46	/* do not use in Kernel */
110 #define IP27_INTR_2		47
111 #define IP27_INTR_3		48
112 #define IP27_INTR_4		49
113 #define IP27_INTR_5		50
114 #define IP27_INTR_6		51
115 #define IP27_INTR_7		52
116 
117 #define BRIDGE_ERROR_INTR	53	/* Setup by PROM to catch	*/
118 					/* Bridge Errors */
119 #define DEBUG_INTR_A		54
120 #define DEBUG_INTR_B		55	/* Used by symmon to stop all cpus */
121 #define IO_ERROR_INTR		57	/* Setup by PROM */
122 #define CLK_ERR_INTR		58
123 #define COR_ERR_INTR_A		59
124 #define COR_ERR_INTR_B		60
125 #define MD_COR_ERR_INTR		61
126 #define NI_ERROR_INTR		62
127 #define MSC_PANIC_INTR		63
128 
129 #endif /* __ASM_SN_INTR_H */
130