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1 /*
2  * OMAP54xx CM2 instance offset macros
3  *
4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Paul Walmsley (paul@pwsan.com)
7  * Rajendra Nayak (rnayak@ti.com)
8  * Benoit Cousson (b-cousson@ti.com)
9  *
10  * This file is automatically generated from the OMAP hardware databases.
11  * We respectfully ask that any modifications to this file be coordinated
12  * with the public linux-omap@vger.kernel.org mailing list and the
13  * authors above to ensure that the autogeneration scripts are kept
14  * up-to-date with the file contents.
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20 
21 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
22 #define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
23 
24 /* CM2 base address */
25 #define OMAP54XX_CM_CORE_BASE		0x4a008000
26 
27 #define OMAP54XX_CM_CORE_REGADDR(inst, reg)				\
28 	OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))
29 
30 /* CM_CORE instances */
31 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST	0x0000
32 #define OMAP54XX_CM_CORE_CKGEN_INST		0x0100
33 #define OMAP54XX_CM_CORE_COREAON_INST		0x0600
34 #define OMAP54XX_CM_CORE_CORE_INST		0x0700
35 #define OMAP54XX_CM_CORE_IVA_INST		0x1200
36 #define OMAP54XX_CM_CORE_CAM_INST		0x1300
37 #define OMAP54XX_CM_CORE_DSS_INST		0x1400
38 #define OMAP54XX_CM_CORE_GPU_INST		0x1500
39 #define OMAP54XX_CM_CORE_L3INIT_INST		0x1600
40 #define OMAP54XX_CM_CORE_CUSTEFUSE_INST		0x1700
41 #define OMAP54XX_CM_CORE_RESTORE_INST		0x1e00
42 #define OMAP54XX_CM_CORE_INSTR_INST		0x1f00
43 
44 /* CM_CORE clockdomain register offsets (from instance start) */
45 #define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS		0x0000
46 #define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS		0x0000
47 #define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS		0x0100
48 #define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS		0x0200
49 #define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS		0x0300
50 #define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS		0x0400
51 #define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS		0x0500
52 #define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS		0x0600
53 #define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS		0x0700
54 #define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS		0x0800
55 #define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS		0x0900
56 #define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS		0x0a80
57 #define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS			0x0000
58 #define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS			0x0000
59 #define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS			0x0000
60 #define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS			0x0000
61 #define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS		0x0000
62 #define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS	0x0000
63 
64 /* CM_CORE */
65 
66 /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
67 #define OMAP54XX_REVISION_CM_CORE_OFFSET			0x0000
68 #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET		0x0040
69 #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
70 #define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET			0x0080
71 #define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET			0x0084
72 
73 /* CM_CORE.CKGEN_CM_CORE register offsets */
74 #define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET			0x0004
75 #define OMAP54XX_CM_CLKSEL_USB_60MHZ				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004)
76 #define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET			0x0040
77 #define OMAP54XX_CM_CLKMODE_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040)
78 #define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET			0x0044
79 #define OMAP54XX_CM_IDLEST_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044)
80 #define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET			0x0048
81 #define OMAP54XX_CM_AUTOIDLE_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048)
82 #define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET			0x004c
83 #define OMAP54XX_CM_CLKSEL_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c)
84 #define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET			0x0050
85 #define OMAP54XX_CM_DIV_M2_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050)
86 #define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET			0x0054
87 #define OMAP54XX_CM_DIV_M3_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054)
88 #define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET			0x0058
89 #define OMAP54XX_CM_DIV_H11_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058)
90 #define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET			0x005c
91 #define OMAP54XX_CM_DIV_H12_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c)
92 #define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET			0x0060
93 #define OMAP54XX_CM_DIV_H13_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060)
94 #define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET			0x0064
95 #define OMAP54XX_CM_DIV_H14_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064)
96 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET		0x0068
97 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET		0x006c
98 #define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET			0x0080
99 #define OMAP54XX_CM_CLKMODE_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080)
100 #define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET			0x0084
101 #define OMAP54XX_CM_IDLEST_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084)
102 #define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET			0x0088
103 #define OMAP54XX_CM_AUTOIDLE_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088)
104 #define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET			0x008c
105 #define OMAP54XX_CM_CLKSEL_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c)
106 #define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET			0x0090
107 #define OMAP54XX_CM_DIV_M2_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090)
108 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET		0x00a8
109 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET		0x00ac
110 #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET			0x00b4
111 #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4)
112 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET			0x00c0
113 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0)
114 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET			0x00c4
115 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4)
116 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET		0x00c8
117 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8)
118 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET			0x00cc
119 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc)
120 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET			0x00d0
121 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0)
122 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET		0x00e8
123 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET		0x00ec
124 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET		0x00f4
125 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4)
126 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET			0x0100
127 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100)
128 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET			0x0104
129 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104)
130 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET		0x0108
131 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108)
132 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET			0x010c
133 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c)
134 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET			0x0110
135 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110)
136 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET		0x0128
137 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET		0x012c
138 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET		0x0134
139 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134)
140 
141 /* CM_CORE.COREAON_CM_CORE register offsets */
142 #define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET			0x0000
143 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET	0x0028
144 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028)
145 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET	0x0030
146 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030)
147 #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET	0x0038
148 #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038)
149 #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET		0x0040
150 #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040)
151 #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET		0x0050
152 #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050)
153 
154 /* CM_CORE.CORE_CM_CORE register offsets */
155 #define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET			0x0000
156 #define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET			0x0008
157 #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET		0x0020
158 #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020)
159 #define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET			0x0100
160 #define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET			0x0108
161 #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET		0x0120
162 #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120)
163 #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET			0x0128
164 #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128)
165 #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET		0x0130
166 #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130)
167 #define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET			0x0200
168 #define OMAP54XX_CM_IPU_STATICDEP_OFFSET			0x0204
169 #define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET			0x0208
170 #define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET			0x0220
171 #define OMAP54XX_CM_IPU_IPU_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220)
172 #define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET			0x0300
173 #define OMAP54XX_CM_DMA_STATICDEP_OFFSET			0x0304
174 #define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET			0x0308
175 #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET		0x0320
176 #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320)
177 #define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET			0x0400
178 #define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET			0x0420
179 #define OMAP54XX_CM_EMIF_DMM_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420)
180 #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET		0x0428
181 #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428)
182 #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET			0x0430
183 #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430)
184 #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET			0x0438
185 #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438)
186 #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET		0x0440
187 #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440)
188 #define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET			0x0500
189 #define OMAP54XX_CM_C2C_STATICDEP_OFFSET			0x0504
190 #define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET			0x0508
191 #define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET			0x0520
192 #define OMAP54XX_CM_C2C_C2C_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520)
193 #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET		0x0528
194 #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528)
195 #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET		0x0530
196 #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530)
197 #define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET			0x0600
198 #define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET			0x0608
199 #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET			0x0620
200 #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620)
201 #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET		0x0628
202 #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628)
203 #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET		0x0630
204 #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630)
205 #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET		0x0638
206 #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638)
207 #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET		0x0640
208 #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640)
209 #define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET			0x0700
210 #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET		0x0720
211 #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720)
212 #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET		0x0728
213 #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728)
214 #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET		0x0740
215 #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740)
216 #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET		0x0748
217 #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748)
218 #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET	0x0750
219 #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750)
220 #define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET			0x0800
221 #define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET			0x0804
222 #define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET			0x0808
223 #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET			0x0820
224 #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820)
225 #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET		0x0828
226 #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828)
227 #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET			0x0830
228 #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830)
229 #define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET			0x0900
230 #define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET			0x0908
231 #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET		0x0928
232 #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928)
233 #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET		0x0930
234 #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930)
235 #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET			0x0938
236 #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938)
237 #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET			0x0940
238 #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940)
239 #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET			0x0948
240 #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948)
241 #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET			0x0950
242 #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950)
243 #define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET			0x0958
244 #define OMAP54XX_CM_L4PER_ELM_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958)
245 #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET			0x0960
246 #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960)
247 #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET			0x0968
248 #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968)
249 #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET			0x0970
250 #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970)
251 #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET			0x0978
252 #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978)
253 #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET			0x0980
254 #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980)
255 #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET			0x0988
256 #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988)
257 #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET			0x09a0
258 #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0)
259 #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET			0x09a8
260 #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8)
261 #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET			0x09b0
262 #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0)
263 #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET			0x09b8
264 #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8)
265 #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET			0x09c0
266 #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0)
267 #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET			0x09f0
268 #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0)
269 #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET			0x09f8
270 #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8)
271 #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET			0x0a00
272 #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00)
273 #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET			0x0a08
274 #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08)
275 #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET			0x0a10
276 #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10)
277 #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET			0x0a18
278 #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18)
279 #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET			0x0a20
280 #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20)
281 #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET			0x0a28
282 #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28)
283 #define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET			0x0a40
284 #define OMAP54XX_CM_L4PER_UART1_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40)
285 #define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET			0x0a48
286 #define OMAP54XX_CM_L4PER_UART2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48)
287 #define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET			0x0a50
288 #define OMAP54XX_CM_L4PER_UART3_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50)
289 #define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET			0x0a58
290 #define OMAP54XX_CM_L4PER_UART4_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58)
291 #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET			0x0a60
292 #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60)
293 #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET			0x0a68
294 #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68)
295 #define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET			0x0a70
296 #define OMAP54XX_CM_L4PER_UART5_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70)
297 #define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET			0x0a78
298 #define OMAP54XX_CM_L4PER_UART6_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78)
299 #define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET			0x0a80
300 #define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET			0x0a84
301 #define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET			0x0a88
302 #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET			0x0aa0
303 #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0)
304 #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET			0x0aa8
305 #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8)
306 #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET		0x0ab0
307 #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0)
308 #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET			0x0ab8
309 #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8)
310 #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET			0x0ac0
311 #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0)
312 #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET		0x0ac8
313 #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8)
314 #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET		0x0ad8
315 #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8)
316 
317 /* CM_CORE.IVA_CM_CORE register offsets */
318 #define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET			0x0000
319 #define OMAP54XX_CM_IVA_STATICDEP_OFFSET			0x0004
320 #define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET			0x0008
321 #define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET			0x0020
322 #define OMAP54XX_CM_IVA_IVA_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020)
323 #define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET			0x0028
324 #define OMAP54XX_CM_IVA_SL2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028)
325 
326 /* CM_CORE.CAM_CM_CORE register offsets */
327 #define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET			0x0000
328 #define OMAP54XX_CM_CAM_STATICDEP_OFFSET			0x0004
329 #define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET			0x0008
330 #define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET			0x0020
331 #define OMAP54XX_CM_CAM_ISS_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020)
332 #define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET			0x0028
333 #define OMAP54XX_CM_CAM_FDIF_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028)
334 #define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET			0x0030
335 #define OMAP54XX_CM_CAM_CAL_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030)
336 
337 /* CM_CORE.DSS_CM_CORE register offsets */
338 #define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET			0x0000
339 #define OMAP54XX_CM_DSS_STATICDEP_OFFSET			0x0004
340 #define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET			0x0008
341 #define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET			0x0020
342 #define OMAP54XX_CM_DSS_DSS_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020)
343 #define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET			0x0030
344 #define OMAP54XX_CM_DSS_BB2D_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030)
345 
346 /* CM_CORE.GPU_CM_CORE register offsets */
347 #define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET			0x0000
348 #define OMAP54XX_CM_GPU_STATICDEP_OFFSET			0x0004
349 #define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET			0x0008
350 #define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET			0x0020
351 #define OMAP54XX_CM_GPU_GPU_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020)
352 
353 /* CM_CORE.L3INIT_CM_CORE register offsets */
354 #define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET			0x0000
355 #define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET			0x0004
356 #define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET			0x0008
357 #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET			0x0028
358 #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028)
359 #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET			0x0030
360 #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030)
361 #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET			0x0038
362 #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038)
363 #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET		0x0040
364 #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040)
365 #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET		0x0048
366 #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048)
367 #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET		0x0058
368 #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058)
369 #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET		0x0068
370 #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068)
371 #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET	0x0078
372 #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078)
373 #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET			0x0088
374 #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088)
375 #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET		0x00e0
376 #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0)
377 #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET		0x00e8
378 #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8)
379 #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET		0x00f0
380 #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0)
381 
382 /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
383 #define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET			0x0000
384 #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET	0x0020
385 #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
386 
387 #endif
388