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Searched refs:P0_IRST_HARD_TXRX (Results 1 – 1 of 1) sorted by relevance

/arch/mips/netlogic/xlp/
Dahci-init-xlp2.c98 #define P0_IRST_HARD_TXRX BIT(13) /* PHY lane hard reset */ macro
264 sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_TXRX); in nlm_sata_firmware_init()
299 sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_TXRX); in nlm_sata_firmware_init()