Searched refs:PD0 (Results 1 – 8 of 8) sorted by relevance
8 #define PD0 (1 << 0) macro
253 ; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu254 ; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])274 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid277 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
148 <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */
441 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
556 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
690 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
611 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
227 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */