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1 #ifndef _M32700UT_M32700UT_LAN_H
2 #define _M32700UT_M32700UT_LAN_H
3 
4 /*
5  * include/asm-m32r/m32700ut/m32700ut_lan.h
6  *
7  * M32700UT-LAN board
8  *
9  * Copyright (c) 2002	Takeo Takahashi
10  *
11  * This file is subject to the terms and conditions of the GNU General
12  * Public License.  See the file "COPYING" in the main directory of
13  * this archive for more details.
14  */
15 
16 #ifndef __ASSEMBLY__
17 /*
18  * C functions use non-cache address.
19  */
20 #define M32700UT_LAN_BASE	(0x10000000 /* + NONCACHE_OFFSET */)
21 #else
22 #define M32700UT_LAN_BASE	(0x10000000 + NONCACHE_OFFSET)
23 #endif /* __ASSEMBLY__ */
24 
25 /* ICU
26  *  ICUISTS:	status register
27  *  ICUIREQ0: 	request register
28  *  ICUIREQ1: 	request register
29  *  ICUCR3:	control register for CFIREQ# interrupt
30  *  ICUCR4:	control register for CFC Card insert interrupt
31  *  ICUCR5:	control register for CFC Card eject interrupt
32  *  ICUCR6:	control register for external interrupt
33  *  ICUCR11:	control register for MMC Card insert/eject interrupt
34  *  ICUCR13:	control register for SC error interrupt
35  *  ICUCR14:	control register for SC receive interrupt
36  *  ICUCR15:	control register for SC send interrupt
37  *  ICUCR16:	control register for SIO0 receive interrupt
38  *  ICUCR17:	control register for SIO0 send interrupt
39  */
40 #define M32700UT_LAN_IRQ_LAN	(M32700UT_LAN_PLD_IRQ_BASE + 1)	/* LAN */
41 #define M32700UT_LAN_IRQ_I2C	(M32700UT_LAN_PLD_IRQ_BASE + 3)	/* I2C */
42 
43 #define M32700UT_LAN_ICUISTS	__reg16(M32700UT_LAN_BASE + 0xc0002)
44 #define M32700UT_LAN_ICUISTS_VECB_MASK	(0xf000)
45 #define M32700UT_LAN_VECB(x)	((x) & M32700UT_LAN_ICUISTS_VECB_MASK)
46 #define M32700UT_LAN_ICUISTS_ISN_MASK	(0x07c0)
47 #define M32700UT_LAN_ICUISTS_ISN(x)	((x) & M32700UT_LAN_ICUISTS_ISN_MASK)
48 #define M32700UT_LAN_ICUIREQ0	__reg16(M32700UT_LAN_BASE + 0xc0004)
49 #define M32700UT_LAN_ICUCR1	__reg16(M32700UT_LAN_BASE + 0xc0010)
50 #define M32700UT_LAN_ICUCR3	__reg16(M32700UT_LAN_BASE + 0xc0014)
51 
52 /*
53  * AR register on PLD
54  */
55 #define ARVCR0		__reg32(M32700UT_LAN_BASE + 0x40000)
56 #define ARVCR0_VDS		0x00080000
57 #define ARVCR0_RST		0x00010000
58 #define ARVCR1		__reg32(M32700UT_LAN_BASE + 0x40004)
59 #define ARVCR1_QVGA		0x02000000
60 #define ARVCR1_NORMAL		0x01000000
61 #define ARVCR1_HIEN		0x00010000
62 #define ARVHCOUNT	__reg32(M32700UT_LAN_BASE + 0x40008)
63 #define ARDATA		__reg32(M32700UT_LAN_BASE + 0x40010)
64 #define ARINTSEL	__reg32(M32700UT_LAN_BASE + 0x40014)
65 #define ARINTSEL_INT3		0x10000000	/* CPU INT3 */
66 #define ARDATA32	__reg32(M32700UT_LAN_BASE + 0x04040010)	// Block 5
67 /*
68 #define ARINTSEL_SEL2		0x00002000
69 #define ARINTSEL_SEL3		0x00001000
70 #define ARINTSEL_SEL6		0x00000200
71 #define ARINTSEL_SEL7		0x00000100
72 #define ARINTSEL_SEL9		0x00000040
73 #define ARINTSEL_SEL10		0x00000020
74 #define ARINTSEL_SEL11		0x00000010
75 #define ARINTSEL_SEL12		0x00000008
76 */
77 
78 /*
79  * I2C register on PLD
80  */
81 #define PLDI2CCR	__reg32(M32700UT_LAN_BASE + 0x40040)
82 #define	PLDI2CCR_ES0		0x00000001	/* enable I2C interface */
83 #define PLDI2CMOD	__reg32(M32700UT_LAN_BASE + 0x40044)
84 #define PLDI2CMOD_ACKCLK	0x00000200
85 #define PLDI2CMOD_DTWD		0x00000100
86 #define PLDI2CMOD_10BT		0x00000004
87 #define PLDI2CMOD_ATM_NORMAL	0x00000000
88 #define PLDI2CMOD_ATM_AUTO	0x00000003
89 #define PLDI2CACK	__reg32(M32700UT_LAN_BASE + 0x40048)
90 #define PLDI2CACK_ACK		0x00000001
91 #define PLDI2CFREQ	__reg32(M32700UT_LAN_BASE + 0x4004c)
92 #define PLDI2CCND	__reg32(M32700UT_LAN_BASE + 0x40050)
93 #define PLDI2CCND_START		0x00000001
94 #define PLDI2CCND_STOP		0x00000002
95 #define PLDI2CSTEN	__reg32(M32700UT_LAN_BASE + 0x40054)
96 #define PLDI2CSTEN_STEN		0x00000001
97 #define PLDI2CDATA	__reg32(M32700UT_LAN_BASE + 0x40060)
98 #define PLDI2CSTS	__reg32(M32700UT_LAN_BASE + 0x40064)
99 #define PLDI2CSTS_TRX		0x00000020
100 #define PLDI2CSTS_BB		0x00000010
101 #define PLDI2CSTS_NOACK		0x00000001	/* 0:ack, 1:noack */
102 
103 #endif /* _M32700UT_M32700UT_LAN_H */
104