1 #ifndef __ASM_MACH_ADDR_MAP_H 2 #define __ASM_MACH_ADDR_MAP_H 3 4 /* 5 * Chip Selects 6 */ 7 #define PXA_CS0_PHYS 0x00000000 8 #define PXA_CS1_PHYS 0x04000000 9 #define PXA_CS2_PHYS 0x08000000 10 #define PXA_CS3_PHYS 0x0C000000 11 #define PXA_CS4_PHYS 0x10000000 12 #define PXA_CS5_PHYS 0x14000000 13 14 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ 15 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ 16 #define PXA3xx_CS2_PHYS 0x10000000 17 #define PXA3xx_CS3_PHYS 0x14000000 18 19 /* 20 * Peripheral Bus 21 */ 22 #define PERIPH_PHYS 0x40000000 23 #define PERIPH_VIRT IOMEM(0xf2000000) 24 #define PERIPH_SIZE 0x02000000 25 26 /* 27 * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x) 28 */ 29 #define PXA2XX_SMEMC_PHYS 0x48000000 30 #define PXA3XX_SMEMC_PHYS 0x4a000000 31 #define SMEMC_VIRT IOMEM(0xf6000000) 32 #define SMEMC_SIZE 0x00100000 33 34 /* 35 * Dynamic Memory Controller (only on PXA3xx) 36 */ 37 #define DMEMC_PHYS 0x48100000 38 #define DMEMC_VIRT IOMEM(0xf6100000) 39 #define DMEMC_SIZE 0x00100000 40 41 /* 42 * Reserved space for low level debug virtual addresses within 43 * 0xf6200000..0xf6201000 44 */ 45 46 /* 47 * DFI Bus for NAND, PXA3xx only 48 */ 49 #define NAND_PHYS 0x43100000 50 #define NAND_VIRT IOMEM(0xf6300000) 51 #define NAND_SIZE 0x00100000 52 53 /* 54 * Internal Memory Controller (PXA27x and later) 55 */ 56 #define IMEMC_PHYS 0x58000000 57 #define IMEMC_VIRT IOMEM(0xfe000000) 58 #define IMEMC_SIZE 0x00100000 59 60 #endif /* __ASM_MACH_ADDR_MAP_H */ 61