Searched refs:QCA955X_PLL_DDR_CONFIG_REG (Results 1 – 2 of 2) sorted by relevance
| /arch/mips/include/asm/mach-ath79/ | ||
| D | ar71xx_regs.h | 247 #define QCA955X_PLL_DDR_CONFIG_REG 0x04 macro |
| /arch/mips/ath79/ | ||
| D | clock.c | 387 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); in qca955x_clocks_init() |