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Searched refs:RAM (Results 1 – 25 of 62) sorted by relevance

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/arch/arm/mach-socfpga/
DKconfig15 bool "Suspend to RAM on SOCFPGA"
17 Select this if you want to enable Suspend-to-RAM on SOCFPGA
/arch/arm/mach-shmobile/
Dpm-rcar-gen2.c30 #define RAM 0xe6300000 macro
83 boot_vector_addr = RAM; in rcar_gen2_pm_init()
/arch/m68k/
DKconfig.machine325 comment "RAM configuration"
328 hex "Address of the base of RAM"
331 Define the address that RAM starts at. On many platforms this is
333 platforms choose to setup their RAM at other addresses within the
337 hex "Size of RAM (in bytes), or 0 for automatic"
340 Define the size of the system RAM. If you select 0 then the
341 kernel will try to probe the RAM size at runtime. This is not
349 put at the start of RAM, but it doesn't have to be. On ColdFire
380 of RAM, but usually some small offset from it. Define the start
382 processor vectors at the base of RAM and then the start of the
[all …]
/arch/arm/mm/
Dproc-arm740.S77 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
78 ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
85 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
Dproc-arm940.S299 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
300 ldr r7, =CONFIG_DRAM_SIZE >> 12 @ size of RAM (must be >= 4KB)
302 mcr p15, 0, r3, c6, c1, 0 @ set area 1, RAM
/arch/x86/xen/
DKconfig32 Limit paravirtualized user domains to 512GB of RAM.
35 pv-domains with more than 512 GB of RAM. This option controls the
/arch/sh/include/mach-ecovec24/mach/
Dpartner-jet-setup.txt5 LIST "zImage (RAM boot)"
6 LIST "This script can be used to boot the kernel from RAM via JTAG:"
/arch/mn10300/mm/
Dcache-flush-by-tag.S45 # Flush the entire data cache back to RAM
Dcache-inv-by-tag.S151 clr d2 # we're going to clear tag RAM
154 # read the tags from the tag RAM, and if they indicate a valid dirty
159 add d0,a0 # starting dcache tag RAM
Dcache-dbg-flush-by-reg.S25 # Flush the entire data cache back to RAM and invalidate the icache
Dcache-dbg-flush-by-tag.S26 # Flush the entire data cache back to RAM and invalidate the icache
/arch/frv/kernel/
Dhead-uc-fr451.S67 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
87 # GR8 = base of uncovered RAM
88 # GR9 = top of uncovered RAM
/arch/unicore32/configs/
Dunicore32_defconfig8 # Initial RAM filesystem and RAM disk (initramfs/initrd) support
81 # RAM/ROM/Flash chip drivers
/arch/m68k/hp300/
DREADME.hp3006 Currently only 9000/340 machines have been tested. Any amount of RAM should
/arch/cris/arch-v10/
DREADME.mm41 As a comparison, the Linux/i386 2.0 puts the kernel and physical RAM at
44 map through. That changed in 2.2, putting the kernel/physical RAM at
89 It also means that the total physical RAM that can be mapped is 256 MB
90 (kseg_c above). More RAM can be mapped by choosing a different segmentation
103 chunks of memory not possible using the normal kmalloc physical RAM
129 ( base_c, 0x4 ) | // physical RAM cached area
229 get_vm_area(size). After that, physical RAM pages are allocated and put into
/arch/arm/mach-realview/
DKconfig122 RealView boards other than PB1176 have the RAM available at
124 the board supports 512MB of RAM, this option allows the
127 RAM to be used with SPARSEMEM.
/arch/arm/boot/dts/
Dkirkwood-ts219-6281.dts15 /* RAM: 0: 256 MB, 1: 512 MB */
Dkirkwood-ts219-6282.dts25 /* RAM: 0: 256 MB, 1: 512 MB */
Darmada-xp-matrix.dts61 * This board has 4 GB of RAM, but the last 256 MB of
62 * RAM are not usable due to the overlap with the MBus
Dvexpress-v2p-ca9.dts230 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
275 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
289 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
/arch/arm/mach-prima2/
Dsleep.S47 @ the RAM is going to self refresh mode
/arch/m68k/kernel/
Dvmlinux-nommu.lds6 * This linker script is equipped to build either ROM loaded or RAM
/arch/sh/include/mach-kfr2r09/mach/
Dpartner-jet-setup.txt4 LIST "zImage (RAM boot)"
5 LIST "This script can be used to boot the kernel from RAM via JTAG:"
/arch/xtensa/kernel/
Dhead.S231 l32i a4, a2, 0 # start destination (in RAM)
232 l32i a5, a2, 4 # end desination (in RAM)
/arch/powerpc/boot/dts/
Dwii.dts20 * contiguous RAM range and will BUG() if the memreserve is outside
23 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */

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