| /arch/powerpc/xmon/ |
| D | spu-insns.h | 143 APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */
144 APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */
145 APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (wit…
146 APUOP(M_LNOP, RR, 0x001, "lnop", _A0(), 00000, LNOP) /* LNOP no_operation */
147 APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */
148 APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */
149 APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */
150 APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */
151 APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */
160 APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */
[all …]
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| D | spu.h | 31 RR, enumerator
|
| /arch/x86/crypto/ |
| D | sha1_ssse3_asm.S | 132 RR F1,A,B,C,D,E,0
133 RR F1,D,E,A,B,C,2
134 RR F1,B,C,D,E,A,4
135 RR F1,E,A,B,C,D,6
136 RR F1,C,D,E,A,B,8
138 RR F1,A,B,C,D,E,10
139 RR F1,D,E,A,B,C,12
140 RR F1,B,C,D,E,A,14
141 RR F1,E,A,B,C,D,16
142 RR F1,C,D,E,A,B,18
[all …]
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| D | des3_ede-asm_64.S | 457 initial_permutation3(RL, RR);
463 round3(0, RR, RL, load_next_key, __movq);
464 round3(1, RL, RR, load_next_key, __movq);
465 round3(2, RR, RL, load_next_key, __movq);
466 round3(3, RL, RR, load_next_key, __movq);
467 round3(4, RR, RL, load_next_key, __movq);
468 round3(5, RL, RR, load_next_key, __movq);
469 round3(6, RR, RL, load_next_key, __movq);
470 round3(7, RL, RR, load_next_key, __movq);
471 round3(8, RR, RL, load_next_key, __movq);
[all …]
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| D | cast5-avx-x86_64-asm_64.S | 251 round(RL, RR, 0, 1);
252 round(RR, RL, 1, 2);
253 round(RL, RR, 2, 3);
254 round(RR, RL, 3, 1);
255 round(RL, RR, 4, 2);
256 round(RR, RL, 5, 3);
257 round(RL, RR, 6, 1);
258 round(RR, RL, 7, 2);
259 round(RL, RR, 8, 3);
260 round(RR, RL, 9, 1);
[all …]
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| D | sha1_avx2_x86_64_asm.S | 352 .macro RR r macro
507 RR j
523 RR j
537 RR j
561 RR j+80
573 RR j+80
586 RR j+80
604 RR j+80
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| D | twofish-avx-x86_64-asm_64.S | 74 #define RR %xmm15 macro
181 vpslld $1, x, RR; \
183 vpor x, RR, x;
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| /arch/arc/boot/dts/ |
| D | nsimosci_hs_idu.dts | 50 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
66 RR distribute to all cpus */
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| D | nsim_hs_idu.dts | 45 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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| D | vdk_axc003_idu.dtsi | 40 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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| D | axc003_idu.dtsi | 39 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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| /arch/arm/boot/compressed/ |
| D | head.S | 745 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
768 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
|