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Searched refs:RSTMGR_MPUMODRST_CPU1 (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-socfpga/
Dplatsmp.c38 writel(RSTMGR_MPUMODRST_CPU1, in socfpga_boot_secondary()
62 writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + in socfpga_a10_boot_secondary()
Dcore.h35 #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ macro