Searched refs:Reg (Results 1 – 11 of 11) sorted by relevance
| /arch/metag/include/asm/ |
| D | tbx.h | 829 #define TBI_GETREG( Reg ) __extension__ ({\ argument
831 __asm__ volatile ("MOV\t%0," #Reg "\t/* (*TBI_GETREG OK) */" : \
835 #define TBI_SETREG( Reg, Value ) do {\ argument
837 __asm__ volatile ("MOV\t" #Reg ",%0\t/* (*TBI_SETREG OK) */" : \
840 #define TBI_SWAPREG( Reg, Value ) do {\ argument
842 __asm__ volatile ("SWAP\t" #Reg ",%0\t/* (*TBI_SWAPREG OK) */" : \
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| /arch/arm/mach-uniphier/ |
| D | headsmp.S | 21 mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
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| /arch/mips/boot/dts/cavium-octeon/ |
| D | octeon_3xxx.dts | 63 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
65 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
67 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
75 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
77 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
79 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
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| D | octeon_68xx.dts | 64 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
66 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
68 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
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| /arch/m32r/kernel/ |
| D | head.S | 148 st r5, @r4 ; Set MATM Reg(T bit ON)
210 st r5, @r4 ; Set MATM Reg(T bit OFF)
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| /arch/arm/boot/compressed/ |
| D | head-sharpsl.S | 102 .word 0x08010000 @ w100 Chip ID Reg Address
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| /arch/arc/kernel/ |
| D | entry-compact.S | 206 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
261 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
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| D | entry.S | 332 ; NOTE: SP will grow up by size of CALLEE Reg-File
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| /arch/m32r/mm/ |
| D | mmu.S | 326 st r1, @(MPSZ_offset,r0) ; Set MPSZ Reg(Page size 4KB:0 16KB:1 64KB:2)
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| /arch/arm/mm/ |
| D | cache-v7.S | 57 orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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| /arch/m68k/fpsp040/ |
| D | util.S | 636 | | 0 | Size | Dest Reg # |
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