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Searched refs:S3C2410_CS5 (Results 1 – 7 of 7) sorted by relevance

/arch/arm/mach-s3c24xx/
Dvr1000.h38 #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
51 #define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
54 #define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
57 #define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
Dbast.h81 #define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
94 #define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000)
97 #define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000)
100 #define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000)
195 #define BAST_IDE_CS S3C2410_CS5
Dmach-vr1000.c66 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
188 [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000, 4),
189 [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, 0x40),
195 [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, 4),
196 [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, 0x40),
Dmach-bast.c77 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
307 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
308 [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
385 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
386 [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
403 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
Dmach-osiris.c65 .pfn = __phys_to_pfn(S3C2410_CS5),
70 .pfn = __phys_to_pfn(S3C2410_CS5),
Dmach-anubis.c278 [0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
/arch/arm/mach-s3c24xx/include/mach/
Dmap.h134 #define S3C2410_CS5 (0x28000000) macro