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Searched refs:S5P_PAD_RETENTION_UART_LOWPWR (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
Dpmu.c196 { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
297 { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
Dregs-pmu.h102 #define S5P_PAD_RETENTION_UART_LOWPWR 0x1224 macro