1 /* AM33v2 on-board bus controller registers 2 * 3 * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public Licence 8 * as published by the Free Software Foundation; either version 9 * 2 of the Licence, or (at your option) any later version. 10 */ 11 12 #ifndef _ASM_BUSCTL_REGS_H 13 #define _ASM_BUSCTL_REGS_H 14 15 #include <asm/cpu-regs.h> 16 17 #ifdef __KERNEL__ 18 19 /* bus controller registers */ 20 #define BCCR __SYSREG(0xc0002000, u32) /* bus controller control reg */ 21 #define BCCR_B0AD 0x00000003 /* block 0 (80000000-83ffffff) bus allocation */ 22 #define BCCR_B1AD 0x0000000c /* block 1 (84000000-87ffffff) bus allocation */ 23 #define BCCR_B2AD 0x00000030 /* block 2 (88000000-8bffffff) bus allocation */ 24 #define BCCR_B3AD 0x000000c0 /* block 3 (8c000000-8fffffff) bus allocation */ 25 #define BCCR_B4AD 0x00000300 /* block 4 (90000000-93ffffff) bus allocation */ 26 #define BCCR_B5AD 0x00000c00 /* block 5 (94000000-97ffffff) bus allocation */ 27 #define BCCR_B6AD 0x00003000 /* block 6 (98000000-9bffffff) bus allocation */ 28 #define BCCR_B7AD 0x0000c000 /* block 7 (9c000000-9fffffff) bus allocation */ 29 #define BCCR_BxAD_EXBUS 0x0 /* - direct to system bus controller */ 30 #define BCCR_BxAD_OPEXBUS 0x1 /* - direct to memory bus controller */ 31 #define BCCR_BxAD_OCMBUS 0x2 /* - direct to on chip memory */ 32 #define BCCR_API 0x00070000 /* bus arbitration priority */ 33 #define BCCR_API_DMACICD 0x00000000 /* - DMA > CI > CD */ 34 #define BCCR_API_DMACDCI 0x00010000 /* - DMA > CD > CI */ 35 #define BCCR_API_CICDDMA 0x00020000 /* - CI > CD > DMA */ 36 #define BCCR_API_CDCIDMA 0x00030000 /* - CD > CI > DMA */ 37 #define BCCR_API_ROUNDROBIN 0x00040000 /* - round robin */ 38 #define BCCR_BEPRI_DMACICD 0x00c00000 /* bus error address priority */ 39 #define BCCR_BEPRI_DMACDCI 0x00000000 /* - DMA > CI > CD */ 40 #define BCCR_BEPRI_CICDDMA 0x00400000 /* - DMA > CD > CI */ 41 #define BCCR_BEPRI_CDCIDMA 0x00800000 /* - CI > CD > DMA */ 42 #define BCCR_BEPRI 0x00c00000 /* - CD > CI > DMA */ 43 #define BCCR_TMON 0x03000000 /* timeout value settings */ 44 #define BCCR_TMON_16IOCLK 0x00000000 /* - 16 IOCLK cycles */ 45 #define BCCR_TMON_256IOCLK 0x01000000 /* - 256 IOCLK cycles */ 46 #define BCCR_TMON_4096IOCLK 0x02000000 /* - 4096 IOCLK cycles */ 47 #define BCCR_TMON_65536IOCLK 0x03000000 /* - 65536 IOCLK cycles */ 48 #define BCCR_TMOE 0x10000000 /* timeout detection enable */ 49 50 #define BCBERR __SYSREG(0xc0002010, u32) /* bus error source reg */ 51 #define BCBERR_BESB 0x0000001f /* erroneous access destination space */ 52 #define BCBERR_BESB_MON 0x00000001 /* - monitor space */ 53 #define BCBERR_BESB_IO 0x00000002 /* - IO bus */ 54 #define BCBERR_BESB_EX 0x00000004 /* - EX bus */ 55 #define BCBERR_BESB_OPEX 0x00000008 /* - OpEX bus */ 56 #define BCBERR_BESB_OCM 0x00000010 /* - on chip memory */ 57 #define BCBERR_BERW 0x00000100 /* type of access */ 58 #define BCBERR_BERW_WRITE 0x00000000 /* - write */ 59 #define BCBERR_BERW_READ 0x00000100 /* - read */ 60 #define BCBERR_BESD 0x00000200 /* error detector */ 61 #define BCBERR_BESD_BCU 0x00000000 /* - BCU detected error */ 62 #define BCBERR_BESD_SLAVE_BUS 0x00000200 /* - slave bus detected error */ 63 #define BCBERR_BEBST 0x00000400 /* type of access */ 64 #define BCBERR_BEBST_SINGLE 0x00000000 /* - single */ 65 #define BCBERR_BEBST_BURST 0x00000400 /* - burst */ 66 #define BCBERR_BEME 0x00000800 /* multiple bus error flag */ 67 #define BCBERR_BEMR 0x00007000 /* master bus that caused the error */ 68 #define BCBERR_BEMR_NOERROR 0x00000000 /* - no error */ 69 #define BCBERR_BEMR_CI 0x00001000 /* - CPU instruction fetch bus caused error */ 70 #define BCBERR_BEMR_CD 0x00002000 /* - CPU data bus caused error */ 71 #define BCBERR_BEMR_DMA 0x00004000 /* - DMA bus caused error */ 72 73 #define BCBEAR __SYSREGC(0xc0002020, u32) /* bus error address reg */ 74 75 /* system bus controller registers */ 76 #define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32) /* SBC base addr regs */ 77 #define SBBASE_BE 0x00000001 /* bank enable */ 78 #define SBBASE_BAM 0x0000fffe /* bank address mask [31:17] */ 79 #define SBBASE_BBA 0xfffe0000 /* bank base address [31:17] */ 80 81 #define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32) /* SBC bank ctrl0 regs */ 82 #define SBCNTRL0_WEH 0x00000f00 /* write enable hold */ 83 #define SBCNTRL0_REH 0x0000f000 /* read enable hold */ 84 #define SBCNTRL0_RWH 0x000f0000 /* SRW signal hold */ 85 #define SBCNTRL0_CSH 0x00f00000 /* chip select hold */ 86 #define SBCNTRL0_DAH 0x0f000000 /* data hold */ 87 #define SBCNTRL0_ADH 0xf0000000 /* address hold */ 88 89 #define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32) /* SBC bank ctrl1 regs */ 90 #define SBCNTRL1_WED 0x00000f00 /* write enable delay */ 91 #define SBCNTRL1_RED 0x0000f000 /* read enable delay */ 92 #define SBCNTRL1_RWD 0x000f0000 /* SRW signal delay */ 93 #define SBCNTRL1_ASW 0x00f00000 /* address strobe width */ 94 #define SBCNTRL1_CSD 0x0f000000 /* chip select delay */ 95 #define SBCNTRL1_ASD 0xf0000000 /* address strobe delay */ 96 97 #define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32) /* SBC bank ctrl2 regs */ 98 #define SBCNTRL2_WC 0x000000ff /* wait count */ 99 #define SBCNTRL2_BWC 0x00000f00 /* burst wait count */ 100 #define SBCNTRL2_WM 0x01000000 /* wait mode setting */ 101 #define SBCNTRL2_WM_FIXEDWAIT 0x00000000 /* - fixed wait access */ 102 #define SBCNTRL2_WM_HANDSHAKE 0x01000000 /* - handshake access */ 103 #define SBCNTRL2_BM 0x02000000 /* bus synchronisation mode */ 104 #define SBCNTRL2_BM_SYNC 0x00000000 /* - synchronous mode */ 105 #define SBCNTRL2_BM_ASYNC 0x02000000 /* - asynchronous mode */ 106 #define SBCNTRL2_BW 0x04000000 /* bus width */ 107 #define SBCNTRL2_BW_32 0x00000000 /* - 32 bits */ 108 #define SBCNTRL2_BW_16 0x04000000 /* - 16 bits */ 109 #define SBCNTRL2_RWINV 0x08000000 /* R/W signal invert polarity */ 110 #define SBCNTRL2_RWINV_NORM 0x00000000 /* - normal (read high) */ 111 #define SBCNTRL2_RWINV_INV 0x08000000 /* - inverted (read low) */ 112 #define SBCNTRL2_BT 0x70000000 /* bus type setting */ 113 #define SBCNTRL2_BT_SRAM 0x00000000 /* - SRAM interface */ 114 #define SBCNTRL2_BT_ADMUX 0x00000000 /* - addr/data multiplexed interface */ 115 #define SBCNTRL2_BT_BROM 0x00000000 /* - burst ROM interface */ 116 #define SBCNTRL2_BTSE 0x80000000 /* burst enable */ 117 118 /* memory bus controller */ 119 #define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32) /* MBC base addr regs */ 120 #define SDBASE_CE 0x00000001 /* chip enable */ 121 #define SDBASE_CBAM 0x0000fff0 /* chip base address mask [31:20] */ 122 #define SDBASE_CBAM_SHIFT 16 123 #define SDBASE_CBA 0xfff00000 /* chip base address [31:20] */ 124 125 #define SDRAMBUS __SYSREG(0xda000000, u32) /* bus mode control reg */ 126 #define SDRAMBUS_REFEN 0x00000004 /* refresh enable */ 127 #define SDRAMBUS_TRC 0x00000018 /* refresh command delay time */ 128 #define SDRAMBUS_BSTPT 0x00000020 /* burst stop command enable */ 129 #define SDRAMBUS_PONSEQ 0x00000040 /* power on sequence */ 130 #define SDRAMBUS_SELFREQ 0x00000080 /* self-refresh mode request */ 131 #define SDRAMBUS_SELFON 0x00000100 /* self-refresh mode on */ 132 #define SDRAMBUS_SIZE 0x00030000 /* SDRAM size */ 133 #define SDRAMBUS_SIZE_64Mbit 0x00010000 /* 64Mbit SDRAM (x16) */ 134 #define SDRAMBUS_SIZE_128Mbit 0x00020000 /* 128Mbit SDRAM (x16) */ 135 #define SDRAMBUS_SIZE_256Mbit 0x00030000 /* 256Mbit SDRAM (x16) */ 136 #define SDRAMBUS_TRASWAIT 0x000c0000 /* row address precharge command cycle number */ 137 #define SDRAMBUS_REFNUM 0x00300000 /* refresh command number */ 138 #define SDRAMBUS_BSTWAIT 0x00c00000 /* burst stop command cycle */ 139 #define SDRAMBUS_SETWAIT 0x03000000 /* mode register setting command cycle */ 140 #define SDRAMBUS_PREWAIT 0x0c000000 /* precharge command cycle */ 141 #define SDRAMBUS_RASLATE 0x30000000 /* RAS latency */ 142 #define SDRAMBUS_CASLATE 0xc0000000 /* CAS latency */ 143 144 #define SDREFCNT __SYSREG(0xda000004, u32) /* refresh period reg */ 145 #define SDREFCNT_PERI 0x00000fff /* refresh period */ 146 147 #define SDSHDW __SYSREG(0xda000010, u32) /* test reg */ 148 149 #endif /* __KERNEL__ */ 150 151 #endif /* _ASM_BUSCTL_REGS_H */ 152