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Searched refs:SET0 (Results 1 – 2 of 2) sorted by relevance

/arch/mips/loongson64/loongson-3/
Dsmp.c61 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()
63 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()
65 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0); in ipi_set0_regs_init()
67 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0); in ipi_set0_regs_init()
69 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()
71 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()
73 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0); in ipi_set0_regs_init()
75 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0); in ipi_set0_regs_init()
77 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()
79 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()
[all …]
Dsmp.h22 #define SET0 0x08 macro