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Searched refs:SH (Results 1 – 20 of 20) sorted by relevance

/arch/ia64/include/asm/sn/
Dshub_mmr.h469 #define SH_REAL_JUNK_BUS_LED0 shubmmr(SH, REAL_JUNK_BUS_LED0)
470 #define SH_IPI_INT shubmmr(SH, IPI_INT)
471 #define SH_EVENT_OCCURRED shubmmr(SH, EVENT_OCCURRED)
472 #define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS)
473 #define SH_RTC shubmmr(SH, RTC)
474 #define SH_RTC1_INT_CONFIG shubmmr(SH, RTC1_INT_CONFIG)
475 #define SH_RTC1_INT_ENABLE shubmmr(SH, RTC1_INT_ENABLE)
476 #define SH_RTC2_INT_CONFIG shubmmr(SH, RTC2_INT_CONFIG)
477 #define SH_RTC2_INT_ENABLE shubmmr(SH, RTC2_INT_ENABLE)
478 #define SH_RTC3_INT_CONFIG shubmmr(SH, RTC3_INT_CONFIG)
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/arch/sh/
DKconfig.cpu24 Selecting this option will enable support for SH processors that
39 Most SH-3 users will want to say Y here, whereas most SH-4 users will
47 Selecting this option will enable support for SH processors that
67 the store queues integrated in the SH-4 processors.
DKconfig247 # SH-2 Processor Support
254 # SH-2A Processor Support
307 # SH-3 Processor Support
317 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
323 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
329 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
330 if you have a 100 Mhz SH-3 HD6417708R CPU.
336 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
372 # SH-4 Processor Support
378 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
[all …]
/arch/sh/mm/
DKconfig11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
14 On other systems (such as the SH-3 and 4) where an MMU exists,
67 This sets the default memory size assumed by your SH kernel. It can
91 32-bits through the SH-4A PMB. If this is not set, legacy
117 Some SH systems have many various memories scattered around
179 This enables 8kB pages as supported by SH-X2 and later MMUs.
185 This enables 16kB pages on MMU-less SH systems.
191 This enables support for 64kB pages, possible on all SH-4
261 Since there's sill some aliasing issues on SH-4, this option will
/arch/sh/lib64/
Dmemset.S4 ! Fast SH memset
Dcopy_user_memcpy.S2 ! Fast SH memcpy
17 ! into a longword on the SH, so this does a longword read and small
Dmemcpy.S4 ! Fast SH memcpy
19 ! into a longword on the SH, so this does a longword read and small
/arch/sh/boards/
DKconfig91 SH7343 (SH-Mobile 3AS) evaluation board.
127 Select SecureEdge5410 if configuring for a SnapGear SH board.
138 Sales SH-Graphics board.
307 bool "SH-X3 Prototype board"
335 bool "SH-2007 board"
340 SH-2007 is a single-board computer based around SH7780 chip
/arch/h8300/lib/
Dmulsi3.S2 ; mulsi3 for H8/300H - based on Renesas SH implementation
/arch/sh/lib/
Dudiv_qrnnd.S29 !! libgcc routines for the Renesas / SuperH SH CPUs.
Dudivsi3.S29 !! libgcc routines for the Renesas / SuperH SH CPUs.
Dashiftrt.S29 !! libgcc routines for the Renesas / SuperH SH CPUs.
Dashlsi3.S29 !! libgcc routines for the Renesas / SuperH SH CPUs.
Dashrsi3.S29 !! libgcc routines for the Renesas / SuperH SH CPUs.
Dlshrsi3.S29 !! libgcc routines for the Renesas / SuperH SH CPUs.
Dmovmem.S29 !! libgcc routines for the Renesas / SuperH SH CPUs.
Dudivsi3_i4i.S29 !! libgcc routines for the Renesas / SuperH SH CPUs.
/arch/arm/mach-shmobile/
DKconfig95 bool "SH-Mobile AG5 (R8A73A00)"
/arch/powerpc/xmon/
Dppc-opc.c443 #define SH RSO + 1 macro
448 #define SH6 SH + 1
3246 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3247 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3249 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3250 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3252 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3254 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3255 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3256 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
[all …]
/arch/arm/
DKconfig.debug853 via SCIFA4 on Renesas SH-Mobile AG5 (SH73A0).