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Searched refs:SICB_IAR0 (Results 1 – 3 of 3) sorted by relevance

/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h54 #define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */ macro
DcdefBF561.h72 #define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
73 #define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
/arch/blackfin/kernel/
Ddebug-mmrs.c1505 D32(SICB_IAR0); in bfin_debug_mmrs_init()