Home
last modified time | relevance | path

Searched refs:SICB_IMASK0 (Results 1 – 4 of 4) sorted by relevance

/arch/blackfin/mach-bf561/include/mach/
Dblackfin.h34 #define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
35 #define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
DdefBF561.h52 #define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */ macro
DcdefBF561.h68 #define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
69 #define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
/arch/blackfin/kernel/
Ddebug-mmrs.c1513 D32(SICB_IMASK0); in bfin_debug_mmrs_init()