Searched refs:SPI1_CLK (Results 1 – 4 of 4) sorted by relevance
204 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */507 0x1f0 0 /* SPI1_CLK (IOCFG132) */
552 MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false)
1316 #define SPI1_CLK 0xFFC40510 /* SPI1 Clock Rate Register */ macro
166 #define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK)167 #define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val)