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Searched refs:SPORT0_TCR1 (Results 1 – 25 of 34) sorted by relevance

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/arch/blackfin/mach-bf537/boards/
Dcm_bf537e.c160 .start = SPORT0_TCR1,
161 .end = SPORT0_TCR1 + 0xFF,
593 .start = SPORT0_TCR1,
657 .start = SPORT0_TCR1,
Dminotaur.c417 .start = SPORT0_TCR1,
Dstamp.c1450 .start = SPORT0_TCR1,
1451 .end = SPORT0_TCR1 + 0xFF,
2353 .start = SPORT0_TCR1,
2417 .start = SPORT0_TCR1,
Dcm_bf537u.c485 .start = SPORT0_TCR1,
Dtcm_bf537.c487 .start = SPORT0_TCR1,
/arch/blackfin/mach-bf533/boards/
Dstamp.c378 .start = SPORT0_TCR1,
448 .start = SPORT0_TCR1,
Dblackstamp.c272 .start = SPORT0_TCR1,
Dcm_bf533.c299 .start = SPORT0_TCR1,
/arch/blackfin/mach-bf518/boards/
Dtcm-bf518.c500 .start = SPORT0_TCR1,
Dezbrd.c578 .start = SPORT0_TCR1,
/arch/blackfin/mach-bf548/include/mach/
DdefBF547.h38 #define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register … macro
DcdefBF547.h53 #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
54 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h122 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ macro
DcdefBF532.h562 #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
563 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
/arch/blackfin/mach-bf527/boards/
Dad7160eval.c601 .start = SPORT0_TCR1,
Dezbrd.c621 .start = SPORT0_TCR1,
Dtll6527m.c724 .start = SPORT0_TCR1,
Dcm_bf527.c747 .start = SPORT0_TCR1,
Dezkit.c1006 .start = SPORT0_TCR1,
/arch/blackfin/mach-bf538/boards/
Dezkit.c284 .start = SPORT0_TCR1,
/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h160 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ macro
/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h157 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ macro
/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h234 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ macro
/arch/blackfin/mach-bf548/boards/
Dcm_bf548.c560 .start = SPORT0_TCR1,
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h136 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ macro

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