Searched refs:SPRN_L1CSR0 (Results 1 – 5 of 5) sorted by relevance
| /arch/powerpc/kernel/ |
| D | cpu_setup_fsl_booke.S | 33 mfspr r0, SPRN_L1CSR0
39 mtspr SPRN_L1CSR0, r0 /* Disable */
43 mtspr SPRN_L1CSR0, r0 /* Invalidate */
45 1: mfspr r0, SPRN_L1CSR0
52 mtspr SPRN_L1CSR0, r0 /* Enable */
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| D | head_fsl_booke.S | 1145 mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
1151 mtspr SPRN_L1CSR0, r4
1154 1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
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| D | misc_32.S | 318 mfspr r3,SPRN_L1CSR0
321 mtspr SPRN_L1CSR0,r3
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| /arch/powerpc/kvm/ |
| D | e500_emulate.c | 252 case SPRN_L1CSR0: in kvmppc_core_emulate_mtspr_e500()
382 case SPRN_L1CSR0: in kvmppc_core_emulate_mfspr_e500()
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| /arch/powerpc/include/asm/ |
| D | reg_booke.h | 176 #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ macro
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