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Searched refs:SPR_DCCFGR_NCS (Results 1 – 3 of 3) sorted by relevance

/arch/openrisc/kernel/
Dsetup.c184 cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); in setup_cpuinfo()
Dhead.S733 l.andi r26,r24,SPR_DCCFGR_NCS
/arch/openrisc/include/asm/
Dspr_defs.h311 #define SPR_DCCFGR_NCS 0x00000078 macro