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Searched refs:SPR_DMR1_CW5_OR (Results 1 – 1 of 1) sorted by relevance

/arch/openrisc/include/asm/
Dspr_defs.h423 #define SPR_DMR1_CW5_OR 0x00000800 macro
424 #define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)