1 /* 2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef __DOXYGEN__ 16 17 #ifndef __ARCH_SPR_DEF_32_H__ 18 #define __ARCH_SPR_DEF_32_H__ 19 20 #define SPR_AUX_PERF_COUNT_0 0x6005 21 #define SPR_AUX_PERF_COUNT_1 0x6006 22 #define SPR_AUX_PERF_COUNT_CTL 0x6007 23 #define SPR_AUX_PERF_COUNT_STS 0x6008 24 #define SPR_CYCLE_HIGH 0x4e06 25 #define SPR_CYCLE_LOW 0x4e07 26 #define SPR_DMA_BYTE 0x3900 27 #define SPR_DMA_CHUNK_SIZE 0x3901 28 #define SPR_DMA_CTR 0x3902 29 #define SPR_DMA_CTR__REQUEST_MASK 0x1 30 #define SPR_DMA_CTR__SUSPEND_MASK 0x2 31 #define SPR_DMA_DST_ADDR 0x3903 32 #define SPR_DMA_DST_CHUNK_ADDR 0x3904 33 #define SPR_DMA_SRC_ADDR 0x3905 34 #define SPR_DMA_SRC_CHUNK_ADDR 0x3906 35 #define SPR_DMA_STATUS__DONE_MASK 0x1 36 #define SPR_DMA_STATUS__BUSY_MASK 0x2 37 #define SPR_DMA_STATUS__RUNNING_MASK 0x10 38 #define SPR_DMA_STRIDE 0x3907 39 #define SPR_DMA_USER_STATUS 0x3908 40 #define SPR_DONE 0x4e08 41 #define SPR_EVENT_BEGIN 0x4e0d 42 #define SPR_EVENT_END 0x4e0e 43 #define SPR_EX_CONTEXT_0_0 0x4a05 44 #define SPR_EX_CONTEXT_0_1 0x4a06 45 #define SPR_EX_CONTEXT_0_1__PL_SHIFT 0 46 #define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3 47 #define SPR_EX_CONTEXT_0_1__PL_MASK 0x3 48 #define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2 49 #define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1 50 #define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4 51 #define SPR_EX_CONTEXT_1_0 0x4805 52 #define SPR_EX_CONTEXT_1_1 0x4806 53 #define SPR_EX_CONTEXT_1_1__PL_SHIFT 0 54 #define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3 55 #define SPR_EX_CONTEXT_1_1__PL_MASK 0x3 56 #define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 57 #define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 58 #define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 59 #define SPR_EX_CONTEXT_2_0 0x4605 60 #define SPR_EX_CONTEXT_2_1 0x4606 61 #define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 62 #define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 63 #define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 64 #define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 65 #define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 66 #define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 67 #define SPR_FAIL 0x4e09 68 #define SPR_IDN_AVAIL_EN 0x3e05 69 #define SPR_IDN_CA_DATA 0x0b00 70 #define SPR_IDN_DATA_AVAIL 0x0b03 71 #define SPR_IDN_DEADLOCK_TIMEOUT 0x3406 72 #define SPR_IDN_DEMUX_CA_COUNT 0x0a05 73 #define SPR_IDN_DEMUX_COUNT_0 0x0a06 74 #define SPR_IDN_DEMUX_COUNT_1 0x0a07 75 #define SPR_IDN_DEMUX_CTL 0x0a08 76 #define SPR_IDN_DEMUX_QUEUE_SEL 0x0a0a 77 #define SPR_IDN_DEMUX_STATUS 0x0a0b 78 #define SPR_IDN_DEMUX_WRITE_FIFO 0x0a0c 79 #define SPR_IDN_DIRECTION_PROTECT 0x2e05 80 #define SPR_IDN_PENDING 0x0a0e 81 #define SPR_IDN_REFILL_EN 0x0e05 82 #define SPR_IDN_SP_FIFO_DATA 0x0a0f 83 #define SPR_IDN_SP_FIFO_SEL 0x0a10 84 #define SPR_IDN_SP_FREEZE 0x0a11 85 #define SPR_IDN_SP_FREEZE__SP_FRZ_MASK 0x1 86 #define SPR_IDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2 87 #define SPR_IDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4 88 #define SPR_IDN_SP_STATE 0x0a12 89 #define SPR_IDN_TAG_0 0x0a13 90 #define SPR_IDN_TAG_1 0x0a14 91 #define SPR_IDN_TAG_VALID 0x0a15 92 #define SPR_IDN_TILE_COORD 0x0a16 93 #define SPR_INTCTRL_0_STATUS 0x4a07 94 #define SPR_INTCTRL_1_STATUS 0x4807 95 #define SPR_INTCTRL_2_STATUS 0x4607 96 #define SPR_INTERRUPT_CRITICAL_SECTION 0x4e0a 97 #define SPR_INTERRUPT_MASK_0_0 0x4a08 98 #define SPR_INTERRUPT_MASK_0_1 0x4a09 99 #define SPR_INTERRUPT_MASK_1_0 0x4809 100 #define SPR_INTERRUPT_MASK_1_1 0x480a 101 #define SPR_INTERRUPT_MASK_2_0 0x4608 102 #define SPR_INTERRUPT_MASK_2_1 0x4609 103 #define SPR_INTERRUPT_MASK_RESET_0_0 0x4a0a 104 #define SPR_INTERRUPT_MASK_RESET_0_1 0x4a0b 105 #define SPR_INTERRUPT_MASK_RESET_1_0 0x480b 106 #define SPR_INTERRUPT_MASK_RESET_1_1 0x480c 107 #define SPR_INTERRUPT_MASK_RESET_2_0 0x460a 108 #define SPR_INTERRUPT_MASK_RESET_2_1 0x460b 109 #define SPR_INTERRUPT_MASK_SET_0_0 0x4a0c 110 #define SPR_INTERRUPT_MASK_SET_0_1 0x4a0d 111 #define SPR_INTERRUPT_MASK_SET_1_0 0x480d 112 #define SPR_INTERRUPT_MASK_SET_1_1 0x480e 113 #define SPR_INTERRUPT_MASK_SET_2_0 0x460c 114 #define SPR_INTERRUPT_MASK_SET_2_1 0x460d 115 #define SPR_MPL_AUX_PERF_COUNT_SET_0 0x6000 116 #define SPR_MPL_AUX_PERF_COUNT_SET_1 0x6001 117 #define SPR_MPL_AUX_PERF_COUNT_SET_2 0x6002 118 #define SPR_MPL_DMA_CPL_SET_0 0x5800 119 #define SPR_MPL_DMA_CPL_SET_1 0x5801 120 #define SPR_MPL_DMA_CPL_SET_2 0x5802 121 #define SPR_MPL_DMA_NOTIFY_SET_0 0x3800 122 #define SPR_MPL_DMA_NOTIFY_SET_1 0x3801 123 #define SPR_MPL_DMA_NOTIFY_SET_2 0x3802 124 #define SPR_MPL_IDN_ACCESS_SET_0 0x0a00 125 #define SPR_MPL_IDN_ACCESS_SET_1 0x0a01 126 #define SPR_MPL_IDN_ACCESS_SET_2 0x0a02 127 #define SPR_MPL_IDN_AVAIL_SET_0 0x3e00 128 #define SPR_MPL_IDN_AVAIL_SET_1 0x3e01 129 #define SPR_MPL_IDN_AVAIL_SET_2 0x3e02 130 #define SPR_MPL_IDN_CA_SET_0 0x3a00 131 #define SPR_MPL_IDN_CA_SET_1 0x3a01 132 #define SPR_MPL_IDN_CA_SET_2 0x3a02 133 #define SPR_MPL_IDN_COMPLETE_SET_0 0x1200 134 #define SPR_MPL_IDN_COMPLETE_SET_1 0x1201 135 #define SPR_MPL_IDN_COMPLETE_SET_2 0x1202 136 #define SPR_MPL_IDN_FIREWALL_SET_0 0x2e00 137 #define SPR_MPL_IDN_FIREWALL_SET_1 0x2e01 138 #define SPR_MPL_IDN_FIREWALL_SET_2 0x2e02 139 #define SPR_MPL_IDN_REFILL_SET_0 0x0e00 140 #define SPR_MPL_IDN_REFILL_SET_1 0x0e01 141 #define SPR_MPL_IDN_REFILL_SET_2 0x0e02 142 #define SPR_MPL_IDN_TIMER_SET_0 0x3400 143 #define SPR_MPL_IDN_TIMER_SET_1 0x3401 144 #define SPR_MPL_IDN_TIMER_SET_2 0x3402 145 #define SPR_MPL_INTCTRL_0_SET_0 0x4a00 146 #define SPR_MPL_INTCTRL_0_SET_1 0x4a01 147 #define SPR_MPL_INTCTRL_0_SET_2 0x4a02 148 #define SPR_MPL_INTCTRL_1_SET_0 0x4800 149 #define SPR_MPL_INTCTRL_1_SET_1 0x4801 150 #define SPR_MPL_INTCTRL_1_SET_2 0x4802 151 #define SPR_MPL_INTCTRL_2_SET_0 0x4600 152 #define SPR_MPL_INTCTRL_2_SET_1 0x4601 153 #define SPR_MPL_INTCTRL_2_SET_2 0x4602 154 #define SPR_MPL_PERF_COUNT_SET_0 0x4200 155 #define SPR_MPL_PERF_COUNT_SET_1 0x4201 156 #define SPR_MPL_PERF_COUNT_SET_2 0x4202 157 #define SPR_MPL_SN_ACCESS_SET_0 0x0800 158 #define SPR_MPL_SN_ACCESS_SET_1 0x0801 159 #define SPR_MPL_SN_ACCESS_SET_2 0x0802 160 #define SPR_MPL_SN_CPL_SET_0 0x5a00 161 #define SPR_MPL_SN_CPL_SET_1 0x5a01 162 #define SPR_MPL_SN_CPL_SET_2 0x5a02 163 #define SPR_MPL_SN_FIREWALL_SET_0 0x2c00 164 #define SPR_MPL_SN_FIREWALL_SET_1 0x2c01 165 #define SPR_MPL_SN_FIREWALL_SET_2 0x2c02 166 #define SPR_MPL_SN_NOTIFY_SET_0 0x2a00 167 #define SPR_MPL_SN_NOTIFY_SET_1 0x2a01 168 #define SPR_MPL_SN_NOTIFY_SET_2 0x2a02 169 #define SPR_MPL_UDN_ACCESS_SET_0 0x0c00 170 #define SPR_MPL_UDN_ACCESS_SET_1 0x0c01 171 #define SPR_MPL_UDN_ACCESS_SET_2 0x0c02 172 #define SPR_MPL_UDN_AVAIL_SET_0 0x4000 173 #define SPR_MPL_UDN_AVAIL_SET_1 0x4001 174 #define SPR_MPL_UDN_AVAIL_SET_2 0x4002 175 #define SPR_MPL_UDN_CA_SET_0 0x3c00 176 #define SPR_MPL_UDN_CA_SET_1 0x3c01 177 #define SPR_MPL_UDN_CA_SET_2 0x3c02 178 #define SPR_MPL_UDN_COMPLETE_SET_0 0x1400 179 #define SPR_MPL_UDN_COMPLETE_SET_1 0x1401 180 #define SPR_MPL_UDN_COMPLETE_SET_2 0x1402 181 #define SPR_MPL_UDN_FIREWALL_SET_0 0x3000 182 #define SPR_MPL_UDN_FIREWALL_SET_1 0x3001 183 #define SPR_MPL_UDN_FIREWALL_SET_2 0x3002 184 #define SPR_MPL_UDN_REFILL_SET_0 0x1000 185 #define SPR_MPL_UDN_REFILL_SET_1 0x1001 186 #define SPR_MPL_UDN_REFILL_SET_2 0x1002 187 #define SPR_MPL_UDN_TIMER_SET_0 0x3600 188 #define SPR_MPL_UDN_TIMER_SET_1 0x3601 189 #define SPR_MPL_UDN_TIMER_SET_2 0x3602 190 #define SPR_MPL_WORLD_ACCESS_SET_0 0x4e00 191 #define SPR_MPL_WORLD_ACCESS_SET_1 0x4e01 192 #define SPR_MPL_WORLD_ACCESS_SET_2 0x4e02 193 #define SPR_PASS 0x4e0b 194 #define SPR_PERF_COUNT_0 0x4205 195 #define SPR_PERF_COUNT_1 0x4206 196 #define SPR_PERF_COUNT_CTL 0x4207 197 #define SPR_PERF_COUNT_DN_CTL 0x4210 198 #define SPR_PERF_COUNT_STS 0x4208 199 #define SPR_PROC_STATUS 0x4f00 200 #define SPR_SIM_CONTROL 0x4e0c 201 #define SPR_SNCTL 0x0805 202 #define SPR_SNCTL__FRZFABRIC_MASK 0x1 203 #define SPR_SNSTATIC 0x080c 204 #define SPR_SYSTEM_SAVE_0_0 0x4b00 205 #define SPR_SYSTEM_SAVE_0_1 0x4b01 206 #define SPR_SYSTEM_SAVE_0_2 0x4b02 207 #define SPR_SYSTEM_SAVE_0_3 0x4b03 208 #define SPR_SYSTEM_SAVE_1_0 0x4900 209 #define SPR_SYSTEM_SAVE_1_1 0x4901 210 #define SPR_SYSTEM_SAVE_1_2 0x4902 211 #define SPR_SYSTEM_SAVE_1_3 0x4903 212 #define SPR_SYSTEM_SAVE_2_0 0x4700 213 #define SPR_SYSTEM_SAVE_2_1 0x4701 214 #define SPR_SYSTEM_SAVE_2_2 0x4702 215 #define SPR_SYSTEM_SAVE_2_3 0x4703 216 #define SPR_TILE_COORD 0x4c17 217 #define SPR_TILE_RTF_HWM 0x4e10 218 #define SPR_TILE_TIMER_CONTROL 0x3205 219 #define SPR_TILE_WRITE_PENDING 0x4e0f 220 #define SPR_UDN_AVAIL_EN 0x4005 221 #define SPR_UDN_CA_DATA 0x0d00 222 #define SPR_UDN_DATA_AVAIL 0x0d03 223 #define SPR_UDN_DEADLOCK_TIMEOUT 0x3606 224 #define SPR_UDN_DEMUX_CA_COUNT 0x0c05 225 #define SPR_UDN_DEMUX_COUNT_0 0x0c06 226 #define SPR_UDN_DEMUX_COUNT_1 0x0c07 227 #define SPR_UDN_DEMUX_COUNT_2 0x0c08 228 #define SPR_UDN_DEMUX_COUNT_3 0x0c09 229 #define SPR_UDN_DEMUX_CTL 0x0c0a 230 #define SPR_UDN_DEMUX_QUEUE_SEL 0x0c0c 231 #define SPR_UDN_DEMUX_STATUS 0x0c0d 232 #define SPR_UDN_DEMUX_WRITE_FIFO 0x0c0e 233 #define SPR_UDN_DIRECTION_PROTECT 0x3005 234 #define SPR_UDN_PENDING 0x0c10 235 #define SPR_UDN_REFILL_EN 0x1005 236 #define SPR_UDN_SP_FIFO_DATA 0x0c11 237 #define SPR_UDN_SP_FIFO_SEL 0x0c12 238 #define SPR_UDN_SP_FREEZE 0x0c13 239 #define SPR_UDN_SP_FREEZE__SP_FRZ_MASK 0x1 240 #define SPR_UDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2 241 #define SPR_UDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4 242 #define SPR_UDN_SP_STATE 0x0c14 243 #define SPR_UDN_TAG_0 0x0c15 244 #define SPR_UDN_TAG_1 0x0c16 245 #define SPR_UDN_TAG_2 0x0c17 246 #define SPR_UDN_TAG_3 0x0c18 247 #define SPR_UDN_TAG_VALID 0x0c19 248 #define SPR_UDN_TILE_COORD 0x0c1a 249 #define SPR_WATCH_CTL 0x4209 250 #define SPR_WATCH_MASK 0x420a 251 #define SPR_WATCH_VAL 0x420b 252 253 #endif /* !defined(__ARCH_SPR_DEF_32_H__) */ 254 255 #endif /* !defined(__DOXYGEN__) */ 256