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Searched refs:SWD_CLK_DIV_CTRL_SEL (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-omap1/
Dclock.h277 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 macro
Dclock_data.c598 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),