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Searched refs:Ser1SDCR0 (Results 1 – 7 of 7) sorted by relevance

/arch/arm/mach-sa1100/
Dpm.c70 SAVE(Ser1SDCR0); in sa11x0_pm_enter()
104 RESTORE(Ser1SDCR0); in sa11x0_pm_enter()
Dnanoengine.c96 Ser1SDCR0 |= SDCR0_UART; in nanoengine_map_io()
Dshannon.c89 Ser1SDCR0 |= SDCR0_SUS; in shannon_map_io()
Dhackkit.c93 Ser1SDCR0 |= SDCR0_SUS; in hackkit_map_io()
Dbadge4.c313 Ser1SDCR0 |= SDCR0_UART; in badge4_uart_pm()
Dassabet.c643 Ser1SDCR0 |= SDCR0_SUS; in assabet_map_io()
/arch/arm/mach-sa1100/include/mach/
DSA-1100.h428 #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */ macro