Searched refs:State (Results 1 – 8 of 8) sorted by relevance
/arch/metag/kernel/ |
D | traps.c | 194 static void nest_interrupts(TBIRES State, unsigned long mask) in nest_interrupts() argument 212 if (D0_8 && (State.Sig.SaveMask & TBICTX_PRIV_BIT)) { in nest_interrupts() 213 State.Sig.SaveMask |= (D0_8 >> 16); in nest_interrupts() 225 __TBINestInts(State, &dsp_ctx->regs, mask); in nest_interrupts() 228 __TBINestInts(State, NULL, mask); in nest_interrupts() 230 __TBINestInts(State, NULL, mask); in nest_interrupts() 234 void head_end(TBIRES State, unsigned long mask) in head_end() argument 236 unsigned int savemask = (unsigned short)State.Sig.SaveMask; in head_end() 237 unsigned int ctx_savemask = (unsigned short)State.Sig.pCtx->SaveMask; in head_end() 296 State.Sig.SaveMask = savemask; in head_end() [all …]
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D | kick.c | 69 kick_handler(TBIRES State, int SigNum, int Triggers, int Inst, PTBI pTBI) in kick_handler() argument 77 head_end(State, ~INTS_OFF_MASK); in kick_handler() 80 if (State.Sig.SaveMask & TBICTX_PRIV_BIT) in kick_handler() 81 restart_critical_section(State); in kick_handler() 85 old_regs = set_irq_regs((struct pt_regs *)State.Sig.pCtx); in kick_handler() 97 ret = kh->func(State, SigNum, Triggers, Inst, pTBI, &handled); in kick_handler()
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D | smp.c | 618 static TBIRES ipi_handler(TBIRES State, int SigNum, int Triggers, in ipi_handler() argument 623 return State; in ipi_handler()
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/arch/metag/include/asm/ |
D | traps.h | 28 extern void restart_critical_section(TBIRES State); 43 extern TBIRES __TBIUnExpXXX(TBIRES State, int SigNum, int Triggers, int Inst,
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D | tbx.h | 706 typedef TBIRES (*PTBIAPIFN)( TBIRES State, int SigNum, 754 extern TBIRES __TBIHandleDFR ( TBIRES State, int SigNum, 963 TBIRES __TBIUnExpXXX( TBIRES State, int SigNum, 974 TBIRES __TBISyncTrigger( TBIRES State, int Id ); 987 TBIRES __TBIASyncTrigger( TBIRES State ); 1019 void *__TBICtxSave( TBIRES State, void *pExt ); 1020 void *__TBICtxRestore( TBIRES State, void *pExt ); 1038 void *__TBICtxFPUSave( TBIRES State, void *pExt ); 1039 void *__TBICtxFPURestore( TBIRES State, void *pExt ); 1081 TBIRES __TBINestInts( TBIRES State, void *pExt, int NoNestMask ); [all …]
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/arch/x86/crypto/ |
D | aesni-intel_avx-x86_64.S | 216 TMP2 = 16*1 # Temporary storage for AES State 2 (State 1 is stored in an XMM register) 217 TMP3 = 16*2 # Temporary storage for AES State 3 218 TMP4 = 16*3 # Temporary storage for AES State 4 219 TMP5 = 16*4 # Temporary storage for AES State 5 220 TMP6 = 16*5 # Temporary storage for AES State 6 221 TMP7 = 16*6 # Temporary storage for AES State 7 222 TMP8 = 16*7 # Temporary storage for AES State 8
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/arch/arm/ |
D | Kconfig | 1498 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1505 0022A ("Power State Coordination Interface System Software on
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/arch/x86/ |
D | Kconfig | 2328 power manage devices, enter the Standby State, enter the Suspend 2329 State, or take power saving steps in response to CPU Idle calls."
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