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Searched refs:TLBTEMP_BASE_2 (Results 1 – 2 of 2) sorted by relevance

/arch/xtensa/mm/
Dcache.c115 void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr, in copy_user_highpage()
/arch/xtensa/include/asm/
Dpgtable.h74 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE) macro