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Searched refs:TXENABLE (Results 1 – 8 of 8) sorted by relevance

/arch/metag/tbx/
Dtbiroot.S69 MOV D0Re0,TXENABLE /* Which thread are we? */
Dtbictxfpu.S52 MOV D0Ar6, TXENABLE
Dtbipcx.S312 MOV D1Ar3,TXENABLE /* Which thread are we? */
333 MOV D1Ar3,TXENABLE /* Which thread are we? */
/arch/metag/kernel/
Duser_gateway.S41 MOV D1Ar3,TXENABLE
Dhead.S45 XOR TXENABLE,D0Re0,D0Re0
Dsetup.c474 txenable = __core_reg_get(TXENABLE); in show_cpuinfo()
/arch/metag/mm/
Dcache.c208 thread = (__core_reg_get(TXENABLE) & TXENABLE_THREAD_BITS) in metag_phys_data_cache_flush()
353 thread = (__core_reg_get(TXENABLE) & TXENABLE_THREAD_BITS) in metag_phys_code_cache_flush()
/arch/metag/include/asm/
Dmetag_regs.h314 #define TXENABLE CT.0 /* Need to define bit-field values in these */ macro