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/arch/ia64/kernel/
Dperfmon_itanium.h11 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
12 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
13 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
14 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
15 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
16 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
17 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
18 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
19 …REG_CONFIG , 0, 0xf00000003ffffff8UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
20 …REG_CONFIG , 0, 0xf00000003ffffff8UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
[all …]
Dperfmon_generic.h10 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
11 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
12 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
13 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
14 … */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
15 … */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
16 … */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
17 … */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
26 …4 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(4),0UL, 0UL, 0UL}…
27 …5 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(5),0UL, 0UL, 0UL}…
[all …]
Dperfmon_mckinley.h11 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
12 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
13 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
14 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
15 …00000800000UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
16 …NG, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
17 …NG, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
18 …NG, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
19 …ffffffUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
20 …fffffcUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
[all …]
/arch/sparc/include/uapi/asm/
Dpstate.h13 #define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */
14 #define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
15 #define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/
16 #define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */
17 #define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */
18 #define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */
19 #define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
20 #define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
21 #define PSTATE_RED _AC(0x0000000000000020,UL) /* Reset Error Debug. */
22 #define PSTATE_PEF _AC(0x0000000000000010,UL) /* Floating Point Enable.*/
[all …]
/arch/sparc/include/asm/
Ddcu.h7 #define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
8 #define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
9 #define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
10 #define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
11 #define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
12 #define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
13 #define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
14 #define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
15 #define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
16 #define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
[all …]
Dsfafsr.h8 #define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
10 #define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
12 #define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
14 #define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
16 #define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
18 #define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
20 #define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)
22 #define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)
24 #define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
26 #define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)
[all …]
Dlsu.h7 #define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
8 #define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
9 #define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
10 #define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
11 #define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
12 #define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
13 #define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
14 #define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
15 #define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
16 #define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */
[all …]
Dpgtable_64.h34 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
35 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL)
36 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL)
37 #define MODULES_VADDR _AC(0x0000000010000000,UL)
38 #define MODULES_LEN _AC(0x00000000e0000000,UL)
39 #define MODULES_END _AC(0x00000000f0000000,UL)
40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
42 #define VMALLOC_START _AC(0x0000000100000000,UL)
49 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
[all …]
Dmmu_64.h10 #define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
19 #define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
21 #define CTX_PGSZ_8KB _AC(0x0,UL)
22 #define CTX_PGSZ_64KB _AC(0x1,UL)
23 #define CTX_PGSZ_512KB _AC(0x2,UL)
24 #define CTX_PGSZ_4MB _AC(0x3,UL)
25 #define CTX_PGSZ_BITS _AC(0x7,UL)
/arch/arm/mach-spear/include/mach/
Dspear.h21 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
23 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
25 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
28 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
32 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
34 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
35 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
37 #define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000)
49 #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
54 #define PERIP_GRP2_BASE UL(0xB3000000)
[all …]
/arch/arm64/include/asm/
Dkvm_arm.h26 #define HCR_API (UL(1) << 41)
27 #define HCR_APK (UL(1) << 40)
28 #define HCR_ID (UL(1) << 33)
29 #define HCR_CD (UL(1) << 32)
31 #define HCR_RW (UL(1) << HCR_RW_SHIFT)
32 #define HCR_TRVM (UL(1) << 30)
33 #define HCR_HCD (UL(1) << 29)
34 #define HCR_TDZ (UL(1) << 28)
35 #define HCR_TGE (UL(1) << 27)
36 #define HCR_TVM (UL(1) << 26)
[all …]
Dpgtable-hwdef.h59 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
69 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
79 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
87 #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
199 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
206 #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
207 #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
210 #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24))
211 #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24))
212 #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24))
[all …]
Desr.h76 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
79 #define ESR_ELx_IL (UL(1) << 25)
81 #define ESR_ELx_ISV (UL(1) << 24)
83 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
84 #define ESR_ELx_SSE (UL(1) << 21)
86 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
87 #define ESR_ELx_SF (UL(1) << 15)
88 #define ESR_ELx_AR (UL(1) << 14)
89 #define ESR_ELx_EA (UL(1) << 9)
90 #define ESR_ELx_CM (UL(1) << 8)
[all …]
Dmemory.h34 #define UL(x) _AC(x, UL) macro
51 #define VA_START (UL(0xffffffffffffffff) - \
52 (UL(1) << VA_BITS) + 1)
53 #define PAGE_OFFSET (UL(0xffffffffffffffff) - \
54 (UL(1) << (VA_BITS - 1)) + 1)
62 #define TASK_SIZE_64 (UL(1) << VA_BITS)
65 #define TASK_SIZE_32 UL(0x100000000)
81 #define KASAN_SHADOW_SIZE (UL(1) << (VA_BITS - 3))
/arch/mips/include/asm/mach-generic/
Dspaces.h19 #define PHYS_OFFSET _AC(0, UL)
24 #define CAC_BASE _AC(0x40000000, UL)
26 #define CAC_BASE _AC(0x80000000, UL)
29 #define IO_BASE _AC(0xa0000000, UL)
32 #define UNCAC_BASE _AC(0xa0000000, UL)
37 #define MAP_BASE _AC(0x60000000, UL)
39 #define MAP_BASE _AC(0xc0000000, UL)
47 #define HIGHMEM_START _AC(0x20000000, UL)
56 #define CAC_BASE _AC(0x9800000000000000, UL)
58 #define CAC_BASE _AC(0xa800000000000000, UL)
[all …]
/arch/x86/include/asm/
Dpgtable_64_types.h48 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
50 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
52 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
56 #define MAXMEM _AC(__AC(1, UL) << MAX_PHYSMEM_BITS, UL)
57 #define VMALLOC_START _AC(0xffffc90000000000, UL)
58 #define VMALLOC_END _AC(0xffffe8ffffffffff, UL)
59 #define VMEMMAP_START _AC(0xffffea0000000000, UL)
61 #define MODULES_END _AC(0xffffffffff000000, UL)
63 #define ESPFIX_PGD_ENTRY _AC(-2, UL)
65 #define EFI_VA_START ( -4 * (_AC(1, UL) << 30))
[all …]
Ddebugreg.h78 set_debugreg(0UL, 7); in hw_breakpoint_disable()
81 set_debugreg(0UL, 0); in hw_breakpoint_disable()
82 set_debugreg(0UL, 1); in hw_breakpoint_disable()
83 set_debugreg(0UL, 2); in hw_breakpoint_disable()
84 set_debugreg(0UL, 3); in hw_breakpoint_disable()
/arch/x86/kernel/cpu/mtrr/
Dcyrix.c242 {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
243 {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
/arch/sparc/kernel/
Dtraps_32.c175 { ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
176 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
177 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
178 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL };
/arch/arm/include/asm/
Dmemory.h29 #define UL(x) _AC(x, UL) macro
32 #define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
40 #define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
46 #define TASK_SIZE_26 (UL(1) << 26)
94 #define TASK_SIZE UL(0xffffffff)
97 #define TASK_UNMAPPED_BASE UL(0x00000000)
101 #define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
119 #define ITCM_OFFSET UL(0xfffe0000)
120 #define DTCM_OFFSET UL(0xfffe8000)
135 #define PLAT_PHYS_OFFSET UL(CONFIG_PHYS_OFFSET)
/arch/m68k/mm/
Dinit.c124 #define UL(x) ((unsigned long) (x)) in print_memmap() macro
125 #define MLK(b, t) UL(b), UL(t), (UL(t) - UL(b)) >> 10 in print_memmap()
126 #define MLM(b, t) UL(b), UL(t), (UL(t) - UL(b)) >> 20 in print_memmap()
/arch/unicore32/include/mach/
Dmemory.h18 #define PHYS_OFFSET UL(0x00000000)
20 #define VECTORS_BASE UL(0xffff0000)
22 #define KUSER_BASE UL(0x80000000)
52 #define KUSER_VECPAGE_BASE (KUSER_BASE + UL(0x3fff0000))
/arch/mips/include/asm/mach-cavium-octeon/
Dspaces.h15 #define CAC_BASE _AC(0x8000000000000000, UL)
16 #define UNCAC_BASE _AC(0x8000000000000000, UL)
17 #define IO_BASE _AC(0x8000000000000000, UL)
/arch/mips/include/asm/mach-ar7/
Dspaces.h17 #define PAGE_OFFSET _AC(0x94000000, UL)
18 #define PHYS_OFFSET _AC(0x14000000, UL)
20 #define UNCAC_BASE _AC(0xb4000000, UL) /* 0xa0000000 + PHYS_OFFSET */
/arch/mips/include/asm/mach-malta/
Dspaces.h36 #define PAGE_OFFSET _AC(0x0, UL)
37 #define PHYS_OFFSET _AC(0x80000000, UL)
38 #define HIGHMEM_START _AC(0xffff0000, UL)

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