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1 /*
2  * vmx.h: VMX Architecture related definitions
3  * Copyright (c) 2004, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16  * Place - Suite 330, Boston, MA 02111-1307 USA.
17  *
18  * A few random additions are:
19  * Copyright (C) 2006 Qumranet
20  *    Avi Kivity <avi@qumranet.com>
21  *    Yaniv Kamay <yaniv@qumranet.com>
22  *
23  */
24 #ifndef VMX_H
25 #define VMX_H
26 
27 
28 #include <linux/types.h>
29 #include <uapi/asm/vmx.h>
30 
31 /*
32  * Definitions of Primary Processor-Based VM-Execution Controls.
33  */
34 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
35 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
36 #define CPU_BASED_HLT_EXITING                   0x00000080
37 #define CPU_BASED_INVLPG_EXITING                0x00000200
38 #define CPU_BASED_MWAIT_EXITING                 0x00000400
39 #define CPU_BASED_RDPMC_EXITING                 0x00000800
40 #define CPU_BASED_RDTSC_EXITING                 0x00001000
41 #define CPU_BASED_CR3_LOAD_EXITING		0x00008000
42 #define CPU_BASED_CR3_STORE_EXITING		0x00010000
43 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
44 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
45 #define CPU_BASED_TPR_SHADOW                    0x00200000
46 #define CPU_BASED_VIRTUAL_NMI_PENDING		0x00400000
47 #define CPU_BASED_MOV_DR_EXITING                0x00800000
48 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
49 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
50 #define CPU_BASED_MONITOR_TRAP_FLAG             0x08000000
51 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
52 #define CPU_BASED_MONITOR_EXITING               0x20000000
53 #define CPU_BASED_PAUSE_EXITING                 0x40000000
54 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
55 
56 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR	0x0401e172
57 
58 /*
59  * Definitions of Secondary Processor-Based VM-Execution Controls.
60  */
61 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
62 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
63 #define SECONDARY_EXEC_RDTSCP			0x00000008
64 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
65 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
66 #define SECONDARY_EXEC_WBINVD_EXITING		0x00000040
67 #define SECONDARY_EXEC_UNRESTRICTED_GUEST	0x00000080
68 #define SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
69 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
70 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING	0x00000400
71 #define SECONDARY_EXEC_ENABLE_INVPCID		0x00001000
72 #define SECONDARY_EXEC_SHADOW_VMCS              0x00004000
73 #define SECONDARY_EXEC_ENABLE_PML               0x00020000
74 #define SECONDARY_EXEC_XSAVES			0x00100000
75 #define SECONDARY_EXEC_PCOMMIT			0x00200000
76 #define SECONDARY_EXEC_TSC_SCALING              0x02000000
77 
78 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
79 #define PIN_BASED_NMI_EXITING                   0x00000008
80 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
81 #define PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
82 #define PIN_BASED_POSTED_INTR                   0x00000080
83 
84 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR	0x00000016
85 
86 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
87 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
88 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
89 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
90 #define VM_EXIT_SAVE_IA32_PAT			0x00040000
91 #define VM_EXIT_LOAD_IA32_PAT			0x00080000
92 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
93 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
94 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
95 #define VM_EXIT_CLEAR_BNDCFGS                   0x00800000
96 
97 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR	0x00036dff
98 
99 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
100 #define VM_ENTRY_IA32E_MODE                     0x00000200
101 #define VM_ENTRY_SMM                            0x00000400
102 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
103 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
104 #define VM_ENTRY_LOAD_IA32_PAT			0x00004000
105 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
106 #define VM_ENTRY_LOAD_BNDCFGS                   0x00010000
107 
108 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR	0x000011ff
109 
110 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK	0x0000001f
111 #define VMX_MISC_SAVE_EFER_LMA			0x00000020
112 #define VMX_MISC_ACTIVITY_HLT			0x00000040
113 
114 /* VMCS Encodings */
115 enum vmcs_field {
116 	VIRTUAL_PROCESSOR_ID            = 0x00000000,
117 	POSTED_INTR_NV                  = 0x00000002,
118 	GUEST_ES_SELECTOR               = 0x00000800,
119 	GUEST_CS_SELECTOR               = 0x00000802,
120 	GUEST_SS_SELECTOR               = 0x00000804,
121 	GUEST_DS_SELECTOR               = 0x00000806,
122 	GUEST_FS_SELECTOR               = 0x00000808,
123 	GUEST_GS_SELECTOR               = 0x0000080a,
124 	GUEST_LDTR_SELECTOR             = 0x0000080c,
125 	GUEST_TR_SELECTOR               = 0x0000080e,
126 	GUEST_INTR_STATUS               = 0x00000810,
127 	GUEST_PML_INDEX			= 0x00000812,
128 	HOST_ES_SELECTOR                = 0x00000c00,
129 	HOST_CS_SELECTOR                = 0x00000c02,
130 	HOST_SS_SELECTOR                = 0x00000c04,
131 	HOST_DS_SELECTOR                = 0x00000c06,
132 	HOST_FS_SELECTOR                = 0x00000c08,
133 	HOST_GS_SELECTOR                = 0x00000c0a,
134 	HOST_TR_SELECTOR                = 0x00000c0c,
135 	IO_BITMAP_A                     = 0x00002000,
136 	IO_BITMAP_A_HIGH                = 0x00002001,
137 	IO_BITMAP_B                     = 0x00002002,
138 	IO_BITMAP_B_HIGH                = 0x00002003,
139 	MSR_BITMAP                      = 0x00002004,
140 	MSR_BITMAP_HIGH                 = 0x00002005,
141 	VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
142 	VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
143 	VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
144 	VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
145 	VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
146 	VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
147 	PML_ADDRESS			= 0x0000200e,
148 	PML_ADDRESS_HIGH		= 0x0000200f,
149 	TSC_OFFSET                      = 0x00002010,
150 	TSC_OFFSET_HIGH                 = 0x00002011,
151 	VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
152 	VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
153 	APIC_ACCESS_ADDR		= 0x00002014,
154 	APIC_ACCESS_ADDR_HIGH		= 0x00002015,
155 	POSTED_INTR_DESC_ADDR           = 0x00002016,
156 	POSTED_INTR_DESC_ADDR_HIGH      = 0x00002017,
157 	EPT_POINTER                     = 0x0000201a,
158 	EPT_POINTER_HIGH                = 0x0000201b,
159 	EOI_EXIT_BITMAP0                = 0x0000201c,
160 	EOI_EXIT_BITMAP0_HIGH           = 0x0000201d,
161 	EOI_EXIT_BITMAP1                = 0x0000201e,
162 	EOI_EXIT_BITMAP1_HIGH           = 0x0000201f,
163 	EOI_EXIT_BITMAP2                = 0x00002020,
164 	EOI_EXIT_BITMAP2_HIGH           = 0x00002021,
165 	EOI_EXIT_BITMAP3                = 0x00002022,
166 	EOI_EXIT_BITMAP3_HIGH           = 0x00002023,
167 	VMREAD_BITMAP                   = 0x00002026,
168 	VMWRITE_BITMAP                  = 0x00002028,
169 	XSS_EXIT_BITMAP                 = 0x0000202C,
170 	XSS_EXIT_BITMAP_HIGH            = 0x0000202D,
171 	TSC_MULTIPLIER                  = 0x00002032,
172 	TSC_MULTIPLIER_HIGH             = 0x00002033,
173 	GUEST_PHYSICAL_ADDRESS          = 0x00002400,
174 	GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
175 	VMCS_LINK_POINTER               = 0x00002800,
176 	VMCS_LINK_POINTER_HIGH          = 0x00002801,
177 	GUEST_IA32_DEBUGCTL             = 0x00002802,
178 	GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
179 	GUEST_IA32_PAT			= 0x00002804,
180 	GUEST_IA32_PAT_HIGH		= 0x00002805,
181 	GUEST_IA32_EFER			= 0x00002806,
182 	GUEST_IA32_EFER_HIGH		= 0x00002807,
183 	GUEST_IA32_PERF_GLOBAL_CTRL	= 0x00002808,
184 	GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
185 	GUEST_PDPTR0                    = 0x0000280a,
186 	GUEST_PDPTR0_HIGH               = 0x0000280b,
187 	GUEST_PDPTR1                    = 0x0000280c,
188 	GUEST_PDPTR1_HIGH               = 0x0000280d,
189 	GUEST_PDPTR2                    = 0x0000280e,
190 	GUEST_PDPTR2_HIGH               = 0x0000280f,
191 	GUEST_PDPTR3                    = 0x00002810,
192 	GUEST_PDPTR3_HIGH               = 0x00002811,
193 	GUEST_BNDCFGS                   = 0x00002812,
194 	GUEST_BNDCFGS_HIGH              = 0x00002813,
195 	HOST_IA32_PAT			= 0x00002c00,
196 	HOST_IA32_PAT_HIGH		= 0x00002c01,
197 	HOST_IA32_EFER			= 0x00002c02,
198 	HOST_IA32_EFER_HIGH		= 0x00002c03,
199 	HOST_IA32_PERF_GLOBAL_CTRL	= 0x00002c04,
200 	HOST_IA32_PERF_GLOBAL_CTRL_HIGH	= 0x00002c05,
201 	PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
202 	CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
203 	EXCEPTION_BITMAP                = 0x00004004,
204 	PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
205 	PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
206 	CR3_TARGET_COUNT                = 0x0000400a,
207 	VM_EXIT_CONTROLS                = 0x0000400c,
208 	VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
209 	VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
210 	VM_ENTRY_CONTROLS               = 0x00004012,
211 	VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
212 	VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
213 	VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
214 	VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
215 	TPR_THRESHOLD                   = 0x0000401c,
216 	SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
217 	PLE_GAP                         = 0x00004020,
218 	PLE_WINDOW                      = 0x00004022,
219 	VM_INSTRUCTION_ERROR            = 0x00004400,
220 	VM_EXIT_REASON                  = 0x00004402,
221 	VM_EXIT_INTR_INFO               = 0x00004404,
222 	VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
223 	IDT_VECTORING_INFO_FIELD        = 0x00004408,
224 	IDT_VECTORING_ERROR_CODE        = 0x0000440a,
225 	VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
226 	VMX_INSTRUCTION_INFO            = 0x0000440e,
227 	GUEST_ES_LIMIT                  = 0x00004800,
228 	GUEST_CS_LIMIT                  = 0x00004802,
229 	GUEST_SS_LIMIT                  = 0x00004804,
230 	GUEST_DS_LIMIT                  = 0x00004806,
231 	GUEST_FS_LIMIT                  = 0x00004808,
232 	GUEST_GS_LIMIT                  = 0x0000480a,
233 	GUEST_LDTR_LIMIT                = 0x0000480c,
234 	GUEST_TR_LIMIT                  = 0x0000480e,
235 	GUEST_GDTR_LIMIT                = 0x00004810,
236 	GUEST_IDTR_LIMIT                = 0x00004812,
237 	GUEST_ES_AR_BYTES               = 0x00004814,
238 	GUEST_CS_AR_BYTES               = 0x00004816,
239 	GUEST_SS_AR_BYTES               = 0x00004818,
240 	GUEST_DS_AR_BYTES               = 0x0000481a,
241 	GUEST_FS_AR_BYTES               = 0x0000481c,
242 	GUEST_GS_AR_BYTES               = 0x0000481e,
243 	GUEST_LDTR_AR_BYTES             = 0x00004820,
244 	GUEST_TR_AR_BYTES               = 0x00004822,
245 	GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
246 	GUEST_ACTIVITY_STATE            = 0X00004826,
247 	GUEST_SYSENTER_CS               = 0x0000482A,
248 	VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
249 	HOST_IA32_SYSENTER_CS           = 0x00004c00,
250 	CR0_GUEST_HOST_MASK             = 0x00006000,
251 	CR4_GUEST_HOST_MASK             = 0x00006002,
252 	CR0_READ_SHADOW                 = 0x00006004,
253 	CR4_READ_SHADOW                 = 0x00006006,
254 	CR3_TARGET_VALUE0               = 0x00006008,
255 	CR3_TARGET_VALUE1               = 0x0000600a,
256 	CR3_TARGET_VALUE2               = 0x0000600c,
257 	CR3_TARGET_VALUE3               = 0x0000600e,
258 	EXIT_QUALIFICATION              = 0x00006400,
259 	GUEST_LINEAR_ADDRESS            = 0x0000640a,
260 	GUEST_CR0                       = 0x00006800,
261 	GUEST_CR3                       = 0x00006802,
262 	GUEST_CR4                       = 0x00006804,
263 	GUEST_ES_BASE                   = 0x00006806,
264 	GUEST_CS_BASE                   = 0x00006808,
265 	GUEST_SS_BASE                   = 0x0000680a,
266 	GUEST_DS_BASE                   = 0x0000680c,
267 	GUEST_FS_BASE                   = 0x0000680e,
268 	GUEST_GS_BASE                   = 0x00006810,
269 	GUEST_LDTR_BASE                 = 0x00006812,
270 	GUEST_TR_BASE                   = 0x00006814,
271 	GUEST_GDTR_BASE                 = 0x00006816,
272 	GUEST_IDTR_BASE                 = 0x00006818,
273 	GUEST_DR7                       = 0x0000681a,
274 	GUEST_RSP                       = 0x0000681c,
275 	GUEST_RIP                       = 0x0000681e,
276 	GUEST_RFLAGS                    = 0x00006820,
277 	GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
278 	GUEST_SYSENTER_ESP              = 0x00006824,
279 	GUEST_SYSENTER_EIP              = 0x00006826,
280 	HOST_CR0                        = 0x00006c00,
281 	HOST_CR3                        = 0x00006c02,
282 	HOST_CR4                        = 0x00006c04,
283 	HOST_FS_BASE                    = 0x00006c06,
284 	HOST_GS_BASE                    = 0x00006c08,
285 	HOST_TR_BASE                    = 0x00006c0a,
286 	HOST_GDTR_BASE                  = 0x00006c0c,
287 	HOST_IDTR_BASE                  = 0x00006c0e,
288 	HOST_IA32_SYSENTER_ESP          = 0x00006c10,
289 	HOST_IA32_SYSENTER_EIP          = 0x00006c12,
290 	HOST_RSP                        = 0x00006c14,
291 	HOST_RIP                        = 0x00006c16,
292 };
293 
294 /*
295  * Interruption-information format
296  */
297 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
298 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
299 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
300 #define INTR_INFO_UNBLOCK_NMI		0x1000		/* 12 */
301 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
302 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
303 
304 #define VECTORING_INFO_VECTOR_MASK           	INTR_INFO_VECTOR_MASK
305 #define VECTORING_INFO_TYPE_MASK        	INTR_INFO_INTR_TYPE_MASK
306 #define VECTORING_INFO_DELIVER_CODE_MASK    	INTR_INFO_DELIVER_CODE_MASK
307 #define VECTORING_INFO_VALID_MASK       	INTR_INFO_VALID_MASK
308 
309 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
310 #define INTR_TYPE_NMI_INTR		(2 << 8) /* NMI */
311 #define INTR_TYPE_HARD_EXCEPTION	(3 << 8) /* processor exception */
312 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
313 #define INTR_TYPE_PRIV_SW_EXCEPTION	(5 << 8) /* ICE breakpoint - undocumented */
314 #define INTR_TYPE_SOFT_EXCEPTION	(6 << 8) /* software exception */
315 
316 /* GUEST_INTERRUPTIBILITY_INFO flags. */
317 #define GUEST_INTR_STATE_STI		0x00000001
318 #define GUEST_INTR_STATE_MOV_SS		0x00000002
319 #define GUEST_INTR_STATE_SMI		0x00000004
320 #define GUEST_INTR_STATE_NMI		0x00000008
321 
322 /* GUEST_ACTIVITY_STATE flags */
323 #define GUEST_ACTIVITY_ACTIVE		0
324 #define GUEST_ACTIVITY_HLT		1
325 #define GUEST_ACTIVITY_SHUTDOWN		2
326 #define GUEST_ACTIVITY_WAIT_SIPI	3
327 
328 /*
329  * Exit Qualifications for MOV for Control Register Access
330  */
331 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
332 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
333 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
334 #define LMSW_SOURCE_DATA_SHIFT 16
335 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
336 #define REG_EAX                         (0 << 8)
337 #define REG_ECX                         (1 << 8)
338 #define REG_EDX                         (2 << 8)
339 #define REG_EBX                         (3 << 8)
340 #define REG_ESP                         (4 << 8)
341 #define REG_EBP                         (5 << 8)
342 #define REG_ESI                         (6 << 8)
343 #define REG_EDI                         (7 << 8)
344 #define REG_R8                         (8 << 8)
345 #define REG_R9                         (9 << 8)
346 #define REG_R10                        (10 << 8)
347 #define REG_R11                        (11 << 8)
348 #define REG_R12                        (12 << 8)
349 #define REG_R13                        (13 << 8)
350 #define REG_R14                        (14 << 8)
351 #define REG_R15                        (15 << 8)
352 
353 /*
354  * Exit Qualifications for MOV for Debug Register Access
355  */
356 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
357 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
358 #define TYPE_MOV_TO_DR                  (0 << 4)
359 #define TYPE_MOV_FROM_DR                (1 << 4)
360 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
361 
362 
363 /*
364  * Exit Qualifications for APIC-Access
365  */
366 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
367 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
368 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
369 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
370 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
371 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
372 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
373 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
374 
375 /* segment AR in VMCS -- these are different from what LAR reports */
376 #define VMX_SEGMENT_AR_L_MASK (1 << 13)
377 
378 #define VMX_AR_TYPE_ACCESSES_MASK 1
379 #define VMX_AR_TYPE_READABLE_MASK (1 << 1)
380 #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
381 #define VMX_AR_TYPE_CODE_MASK (1 << 3)
382 #define VMX_AR_TYPE_MASK 0x0f
383 #define VMX_AR_TYPE_BUSY_64_TSS 11
384 #define VMX_AR_TYPE_BUSY_32_TSS 11
385 #define VMX_AR_TYPE_BUSY_16_TSS 3
386 #define VMX_AR_TYPE_LDT 2
387 
388 #define VMX_AR_UNUSABLE_MASK (1 << 16)
389 #define VMX_AR_S_MASK (1 << 4)
390 #define VMX_AR_P_MASK (1 << 7)
391 #define VMX_AR_L_MASK (1 << 13)
392 #define VMX_AR_DB_MASK (1 << 14)
393 #define VMX_AR_G_MASK (1 << 15)
394 #define VMX_AR_DPL_SHIFT 5
395 #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
396 
397 #define VMX_AR_RESERVD_MASK 0xfffe0f00
398 
399 #define TSS_PRIVATE_MEMSLOT			(KVM_USER_MEM_SLOTS + 0)
400 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT	(KVM_USER_MEM_SLOTS + 1)
401 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT	(KVM_USER_MEM_SLOTS + 2)
402 
403 #define VMX_NR_VPIDS				(1 << 16)
404 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR		0
405 #define VMX_VPID_EXTENT_SINGLE_CONTEXT		1
406 #define VMX_VPID_EXTENT_ALL_CONTEXT		2
407 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL	3
408 
409 #define VMX_EPT_EXTENT_CONTEXT			1
410 #define VMX_EPT_EXTENT_GLOBAL			2
411 #define VMX_EPT_EXTENT_SHIFT			24
412 
413 #define VMX_EPT_EXECUTE_ONLY_BIT		(1ull)
414 #define VMX_EPT_PAGE_WALK_4_BIT			(1ull << 6)
415 #define VMX_EPTP_UC_BIT				(1ull << 8)
416 #define VMX_EPTP_WB_BIT				(1ull << 14)
417 #define VMX_EPT_2MB_PAGE_BIT			(1ull << 16)
418 #define VMX_EPT_1GB_PAGE_BIT			(1ull << 17)
419 #define VMX_EPT_INVEPT_BIT			(1ull << 20)
420 #define VMX_EPT_AD_BIT				    (1ull << 21)
421 #define VMX_EPT_EXTENT_CONTEXT_BIT		(1ull << 25)
422 #define VMX_EPT_EXTENT_GLOBAL_BIT		(1ull << 26)
423 
424 #define VMX_VPID_INVVPID_BIT                    (1ull << 0) /* (32 - 32) */
425 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT     (1ull << 8) /* (40 - 32) */
426 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
427 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
428 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT   (1ull << 11) /* (43 - 32) */
429 
430 #define VMX_EPT_DEFAULT_GAW			3
431 #define VMX_EPT_MAX_GAW				0x4
432 #define VMX_EPT_MT_EPTE_SHIFT			3
433 #define VMX_EPT_GAW_EPTP_SHIFT			3
434 #define VMX_EPT_AD_ENABLE_BIT			(1ull << 6)
435 #define VMX_EPT_DEFAULT_MT			0x6ull
436 #define VMX_EPT_READABLE_MASK			0x1ull
437 #define VMX_EPT_WRITABLE_MASK			0x2ull
438 #define VMX_EPT_EXECUTABLE_MASK			0x4ull
439 #define VMX_EPT_IPAT_BIT    			(1ull << 6)
440 #define VMX_EPT_ACCESS_BIT				(1ull << 8)
441 #define VMX_EPT_DIRTY_BIT				(1ull << 9)
442 
443 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR		0xfffbc000ul
444 
445 
446 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
447 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
448 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
449 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
450 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
451 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
452 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
453 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
454 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
455 #define ASM_VMX_INVEPT		  ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
456 #define ASM_VMX_INVVPID		  ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
457 
458 struct vmx_msr_entry {
459 	u32 index;
460 	u32 reserved;
461 	u64 value;
462 } __aligned(16);
463 
464 /*
465  * Exit Qualifications for entry failure during or after loading guest state
466  */
467 #define ENTRY_FAIL_DEFAULT		0
468 #define ENTRY_FAIL_PDPTE		2
469 #define ENTRY_FAIL_NMI			3
470 #define ENTRY_FAIL_VMCS_LINK_PTR	4
471 
472 /*
473  * VM-instruction error numbers
474  */
475 enum vm_instruction_error_number {
476 	VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
477 	VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
478 	VMXERR_VMCLEAR_VMXON_POINTER = 3,
479 	VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
480 	VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
481 	VMXERR_VMRESUME_AFTER_VMXOFF = 6,
482 	VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
483 	VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
484 	VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
485 	VMXERR_VMPTRLD_VMXON_POINTER = 10,
486 	VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
487 	VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
488 	VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
489 	VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
490 	VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
491 	VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
492 	VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
493 	VMXERR_VMCALL_NONCLEAR_VMCS = 19,
494 	VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
495 	VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
496 	VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
497 	VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
498 	VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
499 	VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
500 	VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
501 };
502 
503 #endif
504