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Searched refs:VS (Results 1 – 3 of 3) sorted by relevance

/arch/mn10300/kernel/
Dkprobes.c100 #define VS (1 << 12) macro
114 /* 1 0 0 0 */ (NE | NC | CC | VS | LT | LE | HI),
115 /* 1 0 0 1 */ (EQ | NC | CC | VS | LT | LE | LS),
116 /* 1 0 1 0 */ (NE | NS | CC | VS | GE | GT | HI),
117 /* 1 0 1 1 */ (EQ | NS | CC | VS | GE | LE | LS),
118 /* 1 1 0 0 */ (NE | NC | CS | VS | LT | LE | LS),
119 /* 1 1 0 1 */ (EQ | NC | CS | VS | LT | LE | LS),
120 /* 1 1 1 0 */ (NE | NS | CS | VS | GE | GT | LS),
121 /* 1 1 1 1 */ (EQ | NS | CS | VS | GE | LE | LS),
/arch/arm/boot/dts/
Dtegra20-paz00.dts565 regulator-name = "+3VS,vdd_pnl";
/arch/powerpc/xmon/
Dppc-opc.c529 #define VS VD macro
4525 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4526 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4527 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4528 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4529 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4536 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4537 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4538 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4539 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },