1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Generic Bus Constants File: sb1250_genbus.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the SB1250's Generic Bus interface 8 * 9 * SB1250 specification level: User's manual 10/21/02 10 * BCM1280 specification level: User's Manual 11/14/03 11 * 12 ********************************************************************* 13 * 14 * Copyright 2000, 2001, 2002, 2003 15 * Broadcom Corporation. All rights reserved. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 ********************************************************************* */ 32 33 34 #ifndef _SB1250_GENBUS_H 35 #define _SB1250_GENBUS_H 36 37 #include <asm/sibyte/sb1250_defs.h> 38 39 /* 40 * Generic Bus Region Configuration Registers (Table 11-4) 41 */ 42 43 #define S_IO_RDY_ACTIVE 0 44 #define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) 45 46 #define S_IO_ENA_RDY 1 47 #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) 48 49 #define S_IO_WIDTH_SEL 2 50 #define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL) 51 #define K_IO_WIDTH_SEL_1 0 52 #define K_IO_WIDTH_SEL_2 1 53 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 54 || SIBYTE_HDR_FEATURE_CHIP(1480) 55 #define K_IO_WIDTH_SEL_1L 2 56 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 57 #define K_IO_WIDTH_SEL_4 3 58 #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) 59 #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL) 60 61 #define S_IO_PARITY_ENA 4 62 #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) 63 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 64 || SIBYTE_HDR_FEATURE_CHIP(1480) 65 #define S_IO_BURST_EN 5 66 #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) 67 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 68 #define S_IO_PARITY_ODD 6 69 #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) 70 #define S_IO_NONMUX 7 71 #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) 72 73 #define S_IO_TIMEOUT 8 74 #define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT) 75 #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT) 76 #define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT) 77 78 /* 79 * Generic Bus Region Size register (Table 11-5) 80 */ 81 82 #define S_IO_MULT_SIZE 0 83 #define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE) 84 #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE) 85 #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE) 86 87 #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ 88 89 /* 90 * Generic Bus Region Address (Table 11-6) 91 */ 92 93 #define S_IO_START_ADDR 0 94 #define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR) 95 #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR) 96 #define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR) 97 98 #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ 99 100 #define M_IO_BLK_CACHE _SB_MAKEMASK1(15) 101 102 103 /* 104 * Generic Bus Timing 0 Registers (Table 11-7) 105 */ 106 107 #define S_IO_ALE_WIDTH 0 108 #define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH) 109 #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH) 110 #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH) 111 112 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 113 || SIBYTE_HDR_FEATURE_CHIP(1480) 114 #define M_IO_EARLY_CS _SB_MAKEMASK1(3) 115 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 116 117 #define S_IO_ALE_TO_CS 4 118 #define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS) 119 #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS) 120 #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS) 121 122 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 123 || SIBYTE_HDR_FEATURE_CHIP(1480) 124 #define S_IO_BURST_WIDTH _SB_MAKE64(6) 125 #define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH) 126 #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH) 127 #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH) 128 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 129 130 #define S_IO_CS_WIDTH 8 131 #define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH) 132 #define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH) 133 #define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH) 134 135 #define S_IO_RDY_SMPLE 13 136 #define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE) 137 #define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE) 138 #define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE) 139 140 141 /* 142 * Generic Bus Timing 1 Registers (Table 11-8) 143 */ 144 145 #define S_IO_ALE_TO_WRITE 0 146 #define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE) 147 #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE) 148 #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE) 149 150 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 151 || SIBYTE_HDR_FEATURE_CHIP(1480) 152 #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) 153 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 154 155 #define S_IO_WRITE_WIDTH 4 156 #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH) 157 #define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH) 158 #define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH) 159 160 #define S_IO_IDLE_CYCLE 8 161 #define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE) 162 #define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE) 163 #define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE) 164 165 #define S_IO_OE_TO_CS 12 166 #define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS) 167 #define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS) 168 #define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS) 169 170 #define S_IO_CS_TO_OE 14 171 #define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE) 172 #define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE) 173 #define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE) 174 175 /* 176 * Generic Bus Interrupt Status Register (Table 11-9) 177 */ 178 179 #define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8) 180 #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) 181 #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) 182 #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) 183 #define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3) 184 #define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4) 185 #define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5) 186 #define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6) 187 #define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7) 188 189 #define M_IO_RD_PAR_INT _SB_MAKEMASK1(9) 190 #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) 191 #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) 192 #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) 193 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 194 #define M_IO_COH_ERR _SB_MAKEMASK1(14) 195 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 196 197 198 /* 199 * Generic Bus Output Drive Control Register 0 (Table 14-18) 200 */ 201 202 #define S_IO_SLEW0 0 203 #define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0) 204 #define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0) 205 #define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0) 206 207 #define S_IO_DRV_A 2 208 #define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A) 209 #define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A) 210 #define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A) 211 212 #define S_IO_DRV_B 6 213 #define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B) 214 #define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B) 215 #define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B) 216 217 #define S_IO_DRV_C 10 218 #define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C) 219 #define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C) 220 #define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C) 221 222 #define S_IO_DRV_D 14 223 #define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D) 224 #define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D) 225 #define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D) 226 227 /* 228 * Generic Bus Output Drive Control Register 1 (Table 14-19) 229 */ 230 231 #define S_IO_DRV_E 2 232 #define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E) 233 #define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E) 234 #define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E) 235 236 #define S_IO_DRV_F 6 237 #define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F) 238 #define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F) 239 #define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F) 240 241 #define S_IO_SLEW1 8 242 #define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1) 243 #define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1) 244 #define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1) 245 246 #define S_IO_DRV_G 10 247 #define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G) 248 #define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G) 249 #define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G) 250 251 #define S_IO_SLEW2 12 252 #define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2) 253 #define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2) 254 #define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2) 255 256 #define S_IO_DRV_H 14 257 #define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H) 258 #define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H) 259 #define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H) 260 261 /* 262 * Generic Bus Output Drive Control Register 2 (Table 14-20) 263 */ 264 265 #define S_IO_DRV_J 2 266 #define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J) 267 #define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J) 268 #define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J) 269 270 #define S_IO_DRV_K 6 271 #define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K) 272 #define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K) 273 #define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K) 274 275 #define S_IO_DRV_L 10 276 #define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L) 277 #define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L) 278 #define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L) 279 280 #define S_IO_DRV_M 14 281 #define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M) 282 #define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M) 283 #define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M) 284 285 /* 286 * Generic Bus Output Drive Control Register 3 (Table 14-21) 287 */ 288 289 #define S_IO_SLEW3 0 290 #define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3) 291 #define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3) 292 #define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3) 293 294 #define S_IO_DRV_N 2 295 #define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N) 296 #define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N) 297 #define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N) 298 299 #define S_IO_DRV_P 6 300 #define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P) 301 #define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P) 302 #define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P) 303 304 #define S_IO_DRV_Q 10 305 #define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q) 306 #define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q) 307 #define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q) 308 309 #define S_IO_DRV_R 14 310 #define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R) 311 #define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R) 312 #define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R) 313 314 315 /* 316 * PCMCIA configuration register (Table 12-6) 317 */ 318 319 #define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0) 320 #define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1) 321 #define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2) 322 #define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3) 323 #define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4) 324 #define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5) 325 #define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6) 326 #define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7) 327 #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) 328 #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) 329 330 #if SIBYTE_HDR_FEATURE_CHIP(1480) 331 #define S_PCMCIA_MODE 16 332 #define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE) 333 #define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE) 334 #define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE) 335 336 #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ 337 #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ 338 #define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */ 339 #define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */ 340 #define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */ 341 #define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */ 342 #define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */ 343 #endif 344 345 346 /* 347 * PCMCIA status register (Table 12-7) 348 */ 349 350 #define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0) 351 #define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1) 352 #define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2) 353 #define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3) 354 #define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4) 355 #define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5) 356 #define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6) 357 #define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7) 358 #define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8) 359 #define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9) 360 #define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10) 361 362 /* 363 * GPIO Interrupt Type Register (table 13-3) 364 */ 365 366 #define K_GPIO_INTR_DISABLE 0 367 #define K_GPIO_INTR_EDGE 1 368 #define K_GPIO_INTR_LEVEL 2 369 #define K_GPIO_INTR_SPLIT 3 370 371 #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) 372 #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n)) 373 #define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n)) 374 #define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n)) 375 376 #define S_GPIO_INTR_TYPE0 0 377 #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0) 378 #define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0) 379 #define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0) 380 381 #define S_GPIO_INTR_TYPE2 2 382 #define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2) 383 #define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2) 384 #define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2) 385 386 #define S_GPIO_INTR_TYPE4 4 387 #define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4) 388 #define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4) 389 #define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4) 390 391 #define S_GPIO_INTR_TYPE6 6 392 #define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6) 393 #define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6) 394 #define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6) 395 396 #define S_GPIO_INTR_TYPE8 8 397 #define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8) 398 #define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8) 399 #define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8) 400 401 #define S_GPIO_INTR_TYPE10 10 402 #define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10) 403 #define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10) 404 #define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10) 405 406 #define S_GPIO_INTR_TYPE12 12 407 #define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12) 408 #define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12) 409 #define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12) 410 411 #define S_GPIO_INTR_TYPE14 14 412 #define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14) 413 #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14) 414 #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14) 415 416 #if SIBYTE_HDR_FEATURE_CHIP(1480) 417 418 /* 419 * GPIO Interrupt Additional Type Register 420 */ 421 422 #define K_GPIO_INTR_BOTHEDGE 0 423 #define K_GPIO_INTR_RISEEDGE 1 424 #define K_GPIO_INTR_UNPRED1 2 425 #define K_GPIO_INTR_UNPRED2 3 426 427 #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) 428 #define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n)) 429 #define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n)) 430 #define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n)) 431 432 #define S_GPIO_INTR_ATYPE0 0 433 #define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0) 434 #define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0) 435 #define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0) 436 437 #define S_GPIO_INTR_ATYPE2 2 438 #define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2) 439 #define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2) 440 #define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2) 441 442 #define S_GPIO_INTR_ATYPE4 4 443 #define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4) 444 #define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4) 445 #define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4) 446 447 #define S_GPIO_INTR_ATYPE6 6 448 #define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6) 449 #define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6) 450 #define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6) 451 452 #define S_GPIO_INTR_ATYPE8 8 453 #define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8) 454 #define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8) 455 #define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8) 456 457 #define S_GPIO_INTR_ATYPE10 10 458 #define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10) 459 #define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10) 460 #define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10) 461 462 #define S_GPIO_INTR_ATYPE12 12 463 #define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12) 464 #define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12) 465 #define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12) 466 467 #define S_GPIO_INTR_ATYPE14 14 468 #define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14) 469 #define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14) 470 #define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14) 471 #endif 472 473 474 #endif 475