Searched refs:X0 (Results 1 – 6 of 6) sorted by relevance
| /arch/arm/crypto/ |
| D | speck-neon-core.S | 24 X0 .req q0
108 vadd.u\n X0, Y0
114 veor X0, ROUND_KEY
130 veor Y0, TMP0, X0
144 veor TMP0, Y0, X0
160 veor X0, ROUND_KEY
166 vsub.u\n X0, Y0
313 _xts128_precrypt_one X0, r12, TMP0
326 _xts64_precrypt_two X0, r12, TMP0
334 vuzp.32 Y0, X0
[all …]
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| /arch/c6x/lib/ |
| D | mpyll.S | 30 ;; P0 = X0*Y0
31 ;; P1 = X0*Y1 + X1*Y0
40 mpy32u .m1x A4,B4,A1:A0 ; X0*Y0
42 || mpy32u .m2x B5,A4,B1:B0 ; X0*Y1 (don't need upper 32-bits)
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| /arch/x86/crypto/ |
| D | sha256-ssse3-asm.S | 74 X0 = %xmm4 define
124 # Rotate values of symbols X0...X3
126 X_ = X0
127 X0 = X1 define
162 paddd X0, XTMP0 # XTMP0 = W[-7] + W[-16]
167 palignr $4, X0, XTMP1 # XTMP1 = W[-15]
277 movdqa XTMP2, X0 # X0 = W[-2] {DDCC}
289 psrld $10, X0 # X0 = W[-2] >> 10 {DDCC}
297 pxor XTMP2, X0 # X0 = s1 {xDxC}
301 pshufb SHUF_DC00, X0 # X0 = s1 {DC00}
[all …]
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| D | sha256-avx-asm.S | 81 X0 = %xmm4 define
131 # Rotate values of symbols X0...X3
133 X_ = X0
134 X0 = X1 define
168 vpaddd X0, XTMP0, XTMP0 # XTMP0 = W[-7] + W[-16]
173 vpalignr $4, X0, X1, XTMP1 # XTMP1 = W[-15]
300 vpaddd XTMP0, XTMP5, X0 # X0 = {W[3], W[2], W[1], W[0]}
385 COPY_XMM_AND_BSWAP X0, 0*16(INP), BYTE_FLIP_MASK
396 vpaddd (TBL), X0, XFER
400 vpaddd 1*16(TBL), X0, XFER
[all …]
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| D | sha256-avx2-asm.S | 68 X0 = %ymm4 define
134 # Rotate values of symbols X0...X3
136 X_ = X0
137 X0 = X1 define
173 vpaddd X0, XTMP0, XTMP0 # XTMP0 = W[-7] + W[-16]# y1 = (e >> 6)# S1
182 vpalignr $4, X0, X1, XTMP1 # XTMP1 = W[-15]
346 vpaddd XTMP0, XTMP5, X0 # X0 = {W[3], W[2], W[1], W[0]}
586 vperm2i128 $0x20, XTMP2, XTMP0, X0
600 vpaddd 0*32(TBL, SRND), X0, XFER
604 vpaddd 1*32(TBL, SRND), X0, XFER
[all …]
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| /arch/m68k/ifpsp060/src/ |
| D | ilsp.S | 67 # and therefore does not work exactly like the 680X0 div{s,u}.l #
484 # and therefore does not work exactly like the 680X0 mul{s,u}.l #
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