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Searched refs:__raw_writeq (Results 1 – 25 of 30) sorted by relevance

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/arch/mips/sibyte/common/
Dsb_tbprof.c164 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); in arm_tb()
173 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | in arm_tb()
177 __raw_writeq( in arm_tb()
183 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | in arm_tb()
190 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); in arm_tb()
192 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); in arm_tb()
197 __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); in arm_tb()
211 __raw_writeq(M_SCD_TRACE_CFG_START_READ, in sbprof_tb_intr()
233 __raw_writeq(M_SCD_TRACE_CFG_RESET, in sbprof_tb_intr()
244 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); in sbprof_tb_intr()
[all …]
/arch/mips/kernel/
Dcevt-bcm1480.c52 __raw_writeq(0, cfg); in sibyte_set_periodic()
53 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
54 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
66 __raw_writeq(0, cfg); in sibyte_shutdown()
78 __raw_writeq(0, cfg); in sibyte_next_event()
79 __raw_writeq(delta - 1, init); in sibyte_next_event()
80 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); in sibyte_next_event()
141 __raw_writeq(IMR_IP4_VAL, in sb1480_clockevent_init()
Dcevt-sb1250.c49 __raw_writeq(0, cfg); in sibyte_shutdown()
62 __raw_writeq(0, cfg); in sibyte_set_periodic()
63 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
64 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
77 __raw_writeq(0, cfg); in sibyte_next_event()
78 __raw_writeq(delta - 1, init); in sibyte_next_event()
79 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); in sibyte_next_event()
141 __raw_writeq(IMR_IP4_VAL, in sb1250_clockevent_init()
Dcsrc-sb1250.c67 __raw_writeq(0, in sb1250_clocksource_init()
70 __raw_writeq(SB1250_HPT_VALUE, in sb1250_clocksource_init()
73 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, in sb1250_clocksource_init()
/arch/mips/sibyte/swarm/
Drtc_m41t81.c93 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); in m41t81_read()
94 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE, in m41t81_read()
100 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, in m41t81_read()
108 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in m41t81_read()
120 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); in m41t81_write()
121 __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA)); in m41t81_write()
122 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, in m41t81_write()
130 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in m41t81_write()
135 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, in m41t81_write()
Drtc_xicor1241.c67 __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); in xicor_read()
68 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); in xicor_read()
69 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, in xicor_read()
75 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, in xicor_read()
83 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in xicor_read()
95 __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); in xicor_write()
96 __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); in xicor_write()
97 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, in xicor_write()
105 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in xicor_write()
/arch/mips/sibyte/sb1250/
Dirq.c168 __raw_writeq(pending, in ack_sb1250_irq()
243 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
247 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
260 __raw_writeq(IMR_IP3_VAL, in arch_init_irq()
263 __raw_writeq(IMR_IP3_VAL, in arch_init_irq()
268 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
270 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
275 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); in arch_init_irq()
276 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); in arch_init_irq()
Dsmp.c71 __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); in sb1250_send_ipi_single()
/arch/mips/sibyte/bcm1480/
Dirq.c181 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), in ack_bcm1480_irq()
185 …__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1… in ack_bcm1480_irq()
261 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
270 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
284 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + in arch_init_irq()
291 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
293 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
301 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); in arch_init_irq()
305 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); in arch_init_irq()
Dsmp.c81 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); in bcm1480_send_ipi_single()
180 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]); in bcm1480_mailbox_interrupt()
/arch/metag/include/asm/
Dio.h90 #define __raw_writeq __raw_writeq macro
91 static inline void __raw_writeq(u64 b, volatile void __iomem *addr) in __raw_writeq() function
112 #define writeq __raw_writeq
130 #define metag_out64(b, addr) __raw_writeq(b, (volatile void __iomem *)(addr))
/arch/arm64/kernel/
Dio.c64 __raw_writeq(*(u64 *)from, to); in __memcpy_toio()
97 __raw_writeq(qc, dst); in __memset_io()
/arch/arm64/include/asm/
Dio.h58 #define __raw_writeq __raw_writeq macro
59 static inline void __raw_writeq(u64 val, volatile void __iomem *addr) in __raw_writeq() function
128 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
/arch/sparc/include/asm/
Dio_64.h91 #define __raw_writeq __raw_writeq macro
92 static inline void __raw_writeq(u64 q, const volatile void __iomem *addr) in __raw_writeq() function
319 __raw_writeq(q, addr); in sbus_writeq()
/arch/alpha/kernel/
Dio.c134 void __raw_writeq(u64 b, volatile void __iomem *addr) in __raw_writeq() function
146 EXPORT_SYMBOL(__raw_writeq);
196 __raw_writeq(b, addr); in writeq()
483 __raw_writeq(*(const u64 *)from, to); in memcpy_toio()
556 __raw_writeq(c, to); in _memset_c_io()
/arch/s390/include/asm/
Dio.h74 #define __raw_writeq zpci_write_u64 macro
/arch/alpha/include/asm/
Dio.h267 extern void __raw_writeq(u64 b, volatile void __iomem *addr);
462 extern inline void __raw_writeq(u64 b, volatile void __iomem *addr) in __raw_writeq() function
489 __raw_writeq(b, addr); in writeq()
512 #define writeq_relaxed(b, addr) __raw_writeq(b, addr)
/arch/mips/mm/
Dpage.c627 __raw_writeq(base_val, base_reg); in sb1_dma_init()
628 __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg); in sb1_dma_init()
629 __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg); in sb1_dma_init()
645 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); in clear_page()
671 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); in copy_page()
/arch/tile/include/asm/
Dio.h124 static inline void __raw_writeq(u64 val, volatile void __iomem *addr) in __raw_writeq() function
171 #define __raw_writeq(val, addr) _tile_writeq(val, (unsigned long)addr) macro
239 #define writeq __raw_writeq
/arch/parisc/include/asm/
Dio.h174 static inline void __raw_writeq(unsigned long long b, volatile void __iomem *addr) in __raw_writeq() function
210 __raw_writeq(cpu_to_le64(q), addr); in writeq()
/arch/sh/include/asm/
Dio.h31 #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v)) macro
46 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c))
/arch/parisc/kernel/
Dperf.c819 __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul), in perf_write_image()
824 __raw_writeq(*memaddr++, runway + RUNWAY_DEBUG); in perf_write_image()
/arch/x86/include/asm/
Dio.h97 #define __raw_writeq(val, addr) writeq(val, addr) macro
/arch/sh/kernel/
Dio_trapped.c214 __raw_writeq(tmp, dst_addr); in copy_word()
/arch/mips/include/asm/
Dmips-cm.h158 __raw_writeq(value, addr_gcr_##name()); \

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