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Searched refs:alpha_mv (Results 1 – 25 of 38) sorted by relevance

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/arch/alpha/kernel/
Dmachvec_impl.h15 #define IRONGATE_HAE_ADDRESS (&alpha_mv.hae_cache)
16 #define MARVEL_HAE_ADDRESS (&alpha_mv.hae_cache)
17 #define POLARIS_HAE_ADDRESS (&alpha_mv.hae_cache)
18 #define TSUNAMI_HAE_ADDRESS (&alpha_mv.hae_cache)
19 #define TITAN_HAE_ADDRESS (&alpha_mv.hae_cache)
20 #define WILDFIRE_HAE_ADDRESS (&alpha_mv.hae_cache)
23 #define CIA_HAE_ADDRESS (&alpha_mv.hae_cache)
26 #define MCPCIA_HAE_ADDRESS (&alpha_mv.hae_cache)
29 #define T2_HAE_ADDRESS (&alpha_mv.hae_cache)
147 struct alpha_machine_vector alpha_mv __attribute__((alias(#system "_mv"))); \
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Dsys_nautilus.c58 alpha_mv.device_interrupt = srm_device_interrupt; in nautilus_init_irq()
208 bus = pci_scan_bus(0, alpha_mv.pci_ops, hose); in nautilus_init_pci()
242 if (memtop > alpha_mv.min_mem_address) { in nautilus_init_pci()
243 free_reserved_area(__va(alpha_mv.min_mem_address), in nautilus_init_pci()
246 (memtop - alpha_mv.min_mem_address) >> 10); in nautilus_init_pci()
257 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq); in nautilus_init_pci()
Dirq_alpha.c74 alpha_mv.machine_check(vector, la_ptr); in do_entInt()
79 alpha_mv.device_interrupt(vector); in do_entInt()
108 alpha_mv.init_irq(); in init_IRQ()
Dsys_sio.c51 alpha_mv.device_interrupt = srm_device_interrupt; in sio_init_irq()
93 orig_route_tab, alpha_mv.sys.sio.route_tab); in sio_pci_route()
101 alpha_mv.sys.sio.route_tab); in sio_pci_route()
182 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq); in noname_map_irq()
201 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq); in p2k_map_irq()
Dsys_titan.c208 if (alpha_using_srm && !alpha_mv.device_interrupt) in titan_init_irq()
209 alpha_mv.device_interrupt = titan_srm_device_interrupt; in titan_init_irq()
210 if (!alpha_mv.device_interrupt) in titan_init_irq()
211 alpha_mv.device_interrupt = titan_device_interrupt; in titan_init_irq()
254 alpha_mv.device_interrupt(vector); in titan_dispatch_irqs()
Dpci_iommu.c163 alpha_mv.mv_pci_tbi(arena->hose, 0, -1); in iommu_arena_find_pages()
227 dma_addr_t dac_offset = alpha_mv.pci_dac_offset; in pci_dac_dma_supported()
280 ret = paddr + alpha_mv.pci_dac_offset; in pci_map_single_1()
291 if (! alpha_mv.mv_pci_tbi) { in pci_map_single_1()
421 alpha_mv.mv_pci_tbi(hose, dma_addr, dma_addr + size - 1); in alpha_pci_unmap_page()
459 if (alpha_mv.mv_pci_tbi || (gfp & GFP_DMA)) in alpha_pci_alloc_coherent()
582 out->dma_address = paddr + alpha_mv.pci_dac_offset; in sg_fill()
680 sg_classify(dev, sg, end, alpha_mv.mv_pci_tbi != 0); in alpha_pci_map_sg()
683 if (alpha_mv.mv_pci_tbi) { in alpha_pci_map_sg()
744 if (! alpha_mv.mv_pci_tbi) in alpha_pci_unmap_sg()
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Dpci.c191 if (alpha_mv.init_pci) in pcibios_init()
192 alpha_mv.init_pci(); in pcibios_init()
339 bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops, in common_init_pci()
357 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq); in common_init_pci()
Dsys_eb64p.c108 alpha_mv = cabriolet_mv; in eb64p_init_irq()
109 alpha_mv.init_irq(); in eb64p_init_irq()
Dsys_alcor.c114 alpha_mv.device_interrupt = srm_device_interrupt; in alcor_init_irq()
242 alpha_mv.sys.cia.gru_int_req_bits = XLT_GRU_INT_REQ_BITS; in alcor_init_pci()
Dsys_takara.c123 alpha_mv.device_interrupt = takara_srm_device_interrupt; in takara_init_irq()
249 alpha_mv.pci_map_irq = takara_map_irq_srm; in takara_init_pci()
Dprocess.c145 if (alpha_mv.kill_arch) in common_shutdown_1()
146 alpha_mv.kill_arch(how->mode); in common_shutdown_1()
257 childregs->hae = alpha_mv.hae_cache, in copy_thread()
Dsetup.c117 struct alpha_machine_vector alpha_mv; variable
118 EXPORT_SYMBOL(alpha_mv);
652 if (vec != &alpha_mv) { in setup_arch()
653 alpha_mv = *vec; in setup_arch()
662 var_name, alpha_mv.vector_name, in setup_arch()
703 srm_hae = *alpha_mv.hae_register; in setup_arch()
704 __set_hae(alpha_mv.hae_cache); in setup_arch()
717 if (alpha_mv.init_arch) in setup_arch()
718 alpha_mv.init_arch(); in setup_arch()
Dsys_sx164.c45 alpha_mv.device_interrupt = srm_device_interrupt; in sx164_init_irq()
Dirq_i8259.c103 # define IACK_SC alpha_mv.iack_sc
Dsys_mikasa.c96 alpha_mv.device_interrupt = srm_device_interrupt; in mikasa_init_irq()
Dcore_cia.c524 alpha_mv.mv_pci_tbi = cia_pci_tbi_try2; in verify_tb_operation()
535 alpha_mv.mv_pci_tbi(arena->hose, 0, -1); in verify_tb_operation()
554 alpha_mv.mv_pci_tbi = NULL; in verify_tb_operation()
766 alpha_mv.pci_dac_offset = 0x200000000UL; in do_init_arch()
767 *(vip)CIA_IOC_PCI_W_DAC = alpha_mv.pci_dac_offset >> 32; in do_init_arch()
/arch/alpha/include/asm/
Dmmzone.h19 (alpha_mv.pa_to_nid \
20 ? alpha_mv.pa_to_nid(pa) \
23 (alpha_mv.node_mem_start \
24 ? alpha_mv.node_mem_start(nid) \
27 (alpha_mv.node_mem_size \
28 ? alpha_mv.node_mem_size(nid) \
Dtopology.h13 if (!alpha_mv.cpuid_to_nid) in cpu_to_node()
16 node = alpha_mv.cpuid_to_nid(cpu); in cpu_to_node()
Dio.h43 alpha_mv.hae_cache = new_hae; in __set_hae()
44 *alpha_mv.hae_register = new_hae; in __set_hae()
47 new_hae = *alpha_mv.hae_register; in __set_hae()
55 if (new_hae != alpha_mv.hae_cache) in set_hae()
149 return alpha_mv.mv_##NAME(addr); \
155 alpha_mv.mv_##NAME(b, addr); \
179 return alpha_mv.mv_ioportmap(a); in REMAP1()
184 return alpha_mv.mv_ioremap(a, s); in generic_ioremap()
189 return alpha_mv.mv_iounmap(a); in generic_iounmap()
194 return alpha_mv.mv_is_ioaddr(a); in generic_is_ioaddr()
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Dpci.h57 #define PCIBIOS_MIN_IO alpha_mv.min_io_address
58 #define PCIBIOS_MIN_MEM alpha_mv.min_mem_address
Dtlbflush.h63 # define flush_tlb_current alpha_mv.mv_flush_tlb_current
64 # define flush_tlb_current_page alpha_mv.mv_flush_tlb_current_page
Dhw_irq.h9 #define ACTUAL_NR_IRQS alpha_mv.nr_irqs
Dmmu_context.h69 # define MAX_ASN (alpha_mv.max_asn)
217 # define switch_mm(a,b,c) alpha_mv.mv_switch_mm((a),(b),(c))
218 # define activate_mm(x,y) alpha_mv.mv_activate_mm((x),(y))
Ddma.h107 # define MAX_ISA_DMA_ADDRESS (alpha_mv.max_isa_dma_address)
125 #define MAX_DMA_ADDRESS (alpha_mv.mv_pci_tbi ? \
Dmachvec.h123 extern struct alpha_machine_vector alpha_mv;

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