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Searched refs:apcr (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-mmp/
Dpm-pxa910.c31 uint32_t awucrm = 0, apcr = 0; in pxa910_set_wake() local
39 apcr |= MPMU_APCR_SLPWP2; in pxa910_set_wake()
44 apcr |= MPMU_APCR_SLPWP3; in pxa910_set_wake()
48 apcr |= MPMU_APCR_SLPWP3; in pxa910_set_wake()
52 apcr |= MPMU_APCR_SLPWP3; in pxa910_set_wake()
57 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
61 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
65 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
69 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
73 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
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Dpm-mmp2.c116 uint32_t idle_cfg, apcr; in mmp2_pm_enter_lowpower_mode() local
119 apcr = __raw_readl(MPMU_PCR_PJ); in mmp2_pm_enter_lowpower_mode()
120 apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD | MPMU_PCR_PJ_APBSD in mmp2_pm_enter_lowpower_mode()
126 apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */ in mmp2_pm_enter_lowpower_mode()
127 apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */ in mmp2_pm_enter_lowpower_mode()
130 apcr |= MPMU_PCR_PJ_SLPEN; in mmp2_pm_enter_lowpower_mode()
133 apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */ in mmp2_pm_enter_lowpower_mode()
136 apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */ in mmp2_pm_enter_lowpower_mode()
137 apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */ in mmp2_pm_enter_lowpower_mode()
139 apcr |= MPMU_PCR_PJ_SPSD; in mmp2_pm_enter_lowpower_mode()
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