| /arch/powerpc/sysdev/ |
| D | axonram.c | 75 struct axon_ram_bank *bank = device->dev.platform_data; in axon_ram_sysfs_ecc() local
77 BUG_ON(!bank); in axon_ram_sysfs_ecc()
79 return sprintf(buf, "%ld\n", bank->ecc_counter); in axon_ram_sysfs_ecc()
93 struct axon_ram_bank *bank = device->dev.platform_data; in axon_ram_irq_handler() local
95 BUG_ON(!bank); in axon_ram_irq_handler()
98 bank->ecc_counter++; in axon_ram_irq_handler()
109 struct axon_ram_bank *bank = bio->bi_bdev->bd_disk->private_data; in axon_ram_make_request() local
116 phys_mem = bank->io_addr + (bio->bi_iter.bi_sector << in axon_ram_make_request()
118 phys_end = bank->io_addr + bank->size; in axon_ram_make_request()
147 struct axon_ram_bank *bank = device->bd_disk->private_data; in axon_ram_direct_access() local
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| /arch/unicore32/include/asm/ |
| D | memblock.h | 29 struct membank bank[NR_BANKS]; member
37 #define bank_pfn_start(bank) __phys_to_pfn((bank)->start) argument
38 #define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) argument
39 #define bank_pfn_size(bank) ((bank)->size >> PAGE_SHIFT) argument
40 #define bank_phys_start(bank) ((bank)->start) argument
41 #define bank_phys_end(bank) ((bank)->start + (bank)->size) argument
42 #define bank_phys_size(bank) ((bank)->size) argument
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| /arch/arm/mach-s3c24xx/ |
| D | iotiming-s3c2412.c | 45 unsigned int bank; in s3c2412_print_timing() local
47 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_print_timing()
48 bt = iot->bank[bank].io_2412; in s3c2412_print_timing()
53 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, in s3c2412_print_timing()
146 int bank; in s3c2412_iotiming_calc() local
149 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_iotiming_calc()
150 bt = iot->bank[bank].io_2412; in s3c2412_iotiming_calc()
157 __func__, bank); in s3c2412_iotiming_calc()
180 int bank; in s3c2412_iotiming_set() local
184 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_iotiming_set()
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| D | iotiming-s3c2410.c | 39 int bank; in s3c2410_print_timing() local
41 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_print_timing()
42 bt = timings->bank[bank].io_2410; in s3c2410_print_timing()
47 "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank, in s3c2410_print_timing()
60 static inline void __iomem *bank_reg(unsigned int bank) in bank_reg() argument
62 return S3C2410_BANKCON0 + (bank << 2); in bank_reg()
366 int bank; in s3c2410_iotiming_calc() local
369 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_iotiming_calc()
370 bankcon = __raw_readl(bank_reg(bank)); in s3c2410_iotiming_calc()
371 bt = iot->bank[bank].io_2410; in s3c2410_iotiming_calc()
[all …]
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| /arch/x86/kernel/cpu/mcheck/ |
| D | mce_amd.c | 85 static inline bool is_shared_bank(int bank) in is_shared_bank() argument
88 return (bank == 4); in is_shared_bank()
111 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) in lvt_interrupt_supported() argument
116 if (bank == 4) in lvt_interrupt_supported()
133 b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
140 b->cpu, apic, b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
256 unsigned int bank, block; in mce_amd_feature_init() local
259 for (bank = 0; bank < mca_cfg.banks; ++bank) { in mce_amd_feature_init()
262 address = MSR_IA32_MCx_MISC(bank); in mce_amd_feature_init()
283 per_cpu(bank_map, cpu) |= (1 << bank); in mce_amd_feature_init()
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| D | mce_intel.c | 152 int bank; in cmci_toggle_interrupt_mode() local
157 for_each_set_bit(bank, owned, MAX_NR_BANKS) { in cmci_toggle_interrupt_mode()
158 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_toggle_interrupt_mode()
165 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_toggle_interrupt_mode()
350 static void __cmci_disable_bank(int bank) in __cmci_disable_bank() argument
354 if (!test_bit(bank, this_cpu_ptr(mce_banks_owned))) in __cmci_disable_bank()
356 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
358 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
359 __clear_bit(bank, this_cpu_ptr(mce_banks_owned)); in __cmci_disable_bank()
410 void cmci_disable_bank(int bank) in cmci_disable_bank() argument
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| /arch/mips/sgi-ip22/ |
| D | ip22-mc.c | 35 static inline unsigned int get_bank_config(int bank) in get_bank_config() argument
37 unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0; in get_bank_config()
38 return bank % 2 ? res & 0xffff : res >> 16; in get_bank_config()
52 struct mem bank[4]; in probe_memory() local
56 for (i = 0; i < ARRAY_SIZE(bank); i++) { in probe_memory()
61 bank[cnt].size = get_bank_size(tmp); in probe_memory()
62 bank[cnt].addr = get_bank_addr(tmp); in probe_memory()
64 i, bank[cnt].size / 1024 / 1024, bank[cnt].addr); in probe_memory()
74 if (bank[i-1].addr > bank[i].addr) { in probe_memory()
75 addr = bank[i].addr; in probe_memory()
[all …]
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| /arch/mips/sgi-ip32/ |
| D | ip32-memory.c | 25 int bank; in prom_meminit() local
29 for (bank=0; bank < CRIME_MAXBANKS; bank++) { in prom_meminit()
30 u64 bankctl = crime->bank_ctrl[bank]; in prom_meminit()
32 if (bank != 0 && base == 0) in prom_meminit()
40 bank, base, size >> 20); in prom_meminit()
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| /arch/xtensa/mm/ |
| D | init.c | 43 sysmem.bank[i].start, sysmem.bank[i].end, in sysmem_dump()
44 (sysmem.bank[i].end - sysmem.bank[i].start) >> 10); in sysmem_dump()
56 if (sysmem.bank[i].start <= start) in find_bank()
57 it = sysmem.bank + i; in find_bank()
72 unsigned n = sysmem.nr_banks - (from - sysmem.bank); in move_banks()
118 it = sysmem.bank; in add_sysmem_bank()
122 if (it - sysmem.bank < sysmem.nr_banks && in add_sysmem_bank()
141 for (i = it + 1 - sysmem.bank; i < sysmem.nr_banks; ++i) in add_sysmem_bank()
142 if (sysmem.bank[i].start - it->start <= sz) { in add_sysmem_bank()
143 if (sz < sysmem.bank[i].end - it->start) in add_sysmem_bank()
[all …]
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| /arch/arm/mach-omap2/ |
| D | powerdomain-common.c | 50 u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank) in omap2_pwrdm_get_mem_bank_onstate_mask() argument
52 switch (bank) { in omap2_pwrdm_get_mem_bank_onstate_mask()
70 u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank) in omap2_pwrdm_get_mem_bank_retst_mask() argument
72 switch (bank) { in omap2_pwrdm_get_mem_bank_retst_mask()
90 u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank) in omap2_pwrdm_get_mem_bank_stst_mask() argument
92 switch (bank) { in omap2_pwrdm_get_mem_bank_stst_mask()
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| D | powerdomain.h | 187 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
188 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
192 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
193 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
194 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
228 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
229 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
234 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
235 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
236 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
[all …]
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| D | prm2xxx_3xxx.c | 114 int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, in omap2_pwrdm_set_mem_onst() argument
119 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); in omap2_pwrdm_set_mem_onst()
127 int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, in omap2_pwrdm_set_mem_retst() argument
132 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); in omap2_pwrdm_set_mem_retst()
140 int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) in omap2_pwrdm_read_mem_pwrst() argument
144 m = omap2_pwrdm_get_mem_bank_stst_mask(bank); in omap2_pwrdm_read_mem_pwrst()
150 int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) in omap2_pwrdm_read_mem_retst() argument
154 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); in omap2_pwrdm_read_mem_retst()
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| D | powerdomain.c | 647 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) in pwrdm_set_mem_onst() argument
654 if (pwrdm->banks < (bank + 1)) in pwrdm_set_mem_onst()
657 if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst))) in pwrdm_set_mem_onst()
661 pwrdm->name, bank, pwrst); in pwrdm_set_mem_onst()
664 ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst); in pwrdm_set_mem_onst()
685 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) in pwrdm_set_mem_retst() argument
692 if (pwrdm->banks < (bank + 1)) in pwrdm_set_mem_retst()
695 if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst))) in pwrdm_set_mem_retst()
699 pwrdm->name, bank, pwrst); in pwrdm_set_mem_retst()
702 ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst); in pwrdm_set_mem_retst()
[all …]
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| D | prm33xx.c | 235 static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, in am33xx_pwrdm_set_mem_onst() argument
240 m = pwrdm->mem_on_mask[bank]; in am33xx_pwrdm_set_mem_onst()
250 static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, in am33xx_pwrdm_set_mem_retst() argument
255 m = pwrdm->mem_ret_mask[bank]; in am33xx_pwrdm_set_mem_retst()
265 static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) in am33xx_pwrdm_read_mem_pwrst() argument
269 m = pwrdm->mem_pwrst_mask[bank]; in am33xx_pwrdm_read_mem_pwrst()
280 static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) in am33xx_pwrdm_read_mem_retst() argument
284 m = pwrdm->mem_retst_mask[bank]; in am33xx_pwrdm_read_mem_retst()
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| /arch/blackfin/kernel/ |
| D | bfin_gpio.c | 547 u16 bank, mask, i; in bfin_gpio_pm_standby_ctrl() local
551 bank = gpio_bank(i); in bfin_gpio_pm_standby_ctrl()
554 bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl); in bfin_gpio_pm_standby_ctrl()
561 int i, bank; in bfin_gpio_pm_hibernate_suspend() local
569 bank = gpio_bank(i); in bfin_gpio_pm_hibernate_suspend()
572 gpio_bank_saved[bank].fer = *port_fer[bank]; in bfin_gpio_pm_hibernate_suspend()
574 gpio_bank_saved[bank].mux = *port_mux[bank]; in bfin_gpio_pm_hibernate_suspend()
576 if (bank == 0) in bfin_gpio_pm_hibernate_suspend()
577 gpio_bank_saved[bank].mux = bfin_read_PORT_MUX(); in bfin_gpio_pm_hibernate_suspend()
580 gpio_bank_saved[bank].data = gpio_array[bank]->data; in bfin_gpio_pm_hibernate_suspend()
[all …]
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| /arch/unicore32/mm/ |
| D | init.c | 70 struct membank *bank = &mi->bank[i]; in show_mem() local
74 pfn1 = bank_pfn_start(bank); in show_mem()
75 pfn2 = bank_pfn_end(bank); in show_mem()
114 struct membank *bank = &mi->bank[i]; in find_limits() local
117 start = bank_pfn_start(bank); in find_limits()
118 end = bank_pfn_end(bank); in find_limits()
124 if (bank->highmem) in find_limits()
246 sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), in uc32_memblock_init()
250 memblock_add(mi->bank[i].start, mi->bank[i].size); in uc32_memblock_init()
356 struct membank *bank = &mi->bank[i]; in free_unused_memmap() local
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| /arch/alpha/kernel/ |
| D | sys_ruffian.c | 183 unsigned long bank_addr, bank, ret = 0; in ruffian_get_bank_size() local
188 bank = *(vulp)bank_addr; in ruffian_get_bank_size()
191 if (bank & 0x01) { in ruffian_get_bank_size()
204 bank = (bank & 0x1e) >> 1; in ruffian_get_bank_size()
205 if (bank < ARRAY_SIZE(size)) in ruffian_get_bank_size()
206 ret = size[bank]; in ruffian_get_bank_size()
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| /arch/x86/platform/scx200/ |
| D | scx200_32.c | 50 int bank; in scx200_init_shadow() local
53 for (bank = 0; bank < 2; ++bank) in scx200_init_shadow()
54 scx200_gpio_shadow[bank] = inl(scx200_gpio_base + 0x10 * bank); in scx200_init_shadow()
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| /arch/mips/jz4740/ |
| D | setup.c | 39 u32 ctrl, bus, bank, rows, cols; in jz4740_detect_mem() local
45 bank = 1 + ((ctrl >> 19) & 1); in jz4740_detect_mem()
50 bus, bank, rows, cols); in jz4740_detect_mem()
53 size = 1 << (bus + bank + cols + rows); in jz4740_detect_mem()
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| /arch/powerpc/boot/dts/ |
| D | media5200.dts | 117 bank-width = <4>; // Width in bytes of the flash bank
118 device-width = <2>; // Two devices on each bank
124 bank-width = <4>; // Width in bytes of the flash bank
125 device-width = <2>; // Two devices on each bank
131 #interrupt-cells = <2>; // 0:bank 1:id; no type field
135 interrupts = <0 0 3 // IRQ bank 0
136 1 1 3>; // IRQ bank 1
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| /arch/unicore32/kernel/ |
| D | setup.c | 136 struct membank *bank = &meminfo.bank[meminfo.nr_banks]; in uc32_add_memory() local
150 bank->start = PAGE_ALIGN(start); in uc32_add_memory()
151 bank->size = size & PAGE_MASK; in uc32_add_memory()
157 if (bank->size == 0) in uc32_add_memory()
207 if (mi->bank[i].size == 0) in request_standard_resources()
212 res->start = mi->bank[i].start; in request_standard_resources()
213 res->end = mi->bank[i].start + mi->bank[i].size - 1; in request_standard_resources()
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| /arch/arm/mach-omap1/ |
| D | irq.c | 70 static inline unsigned int irq_bank_readl(int bank, int offset) in irq_bank_readl() argument
72 return readl_relaxed(irq_banks[bank].va + offset); in irq_bank_readl()
74 static inline void irq_bank_writel(unsigned long value, int bank, int offset) in irq_bank_writel() argument
76 writel_relaxed(value, irq_banks[bank].va + offset); in irq_bank_writel()
104 signed int bank; in omap_irq_set_cfg() local
107 bank = IRQ_BANK(irq); in omap_irq_set_cfg()
109 fiq = bank ? 0 : (fiq & 0x1); in omap_irq_set_cfg()
112 irq_bank_writel(val, bank, offset); in omap_irq_set_cfg()
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| /arch/arm/boot/dts/ |
| D | stih415-pinctrl.dtsi | 61 st,bank-name = "PIO0";
69 st,bank-name = "PIO1";
77 st,bank-name = "PIO2";
85 st,bank-name = "PIO3";
93 st,bank-name = "PIO4";
215 st,bank-name = "PIO5";
223 st,bank-name = "PIO6";
231 st,bank-name = "PIO7";
239 st,bank-name = "PIO8";
247 st,bank-name = "PIO9";
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| D | stih416-pinctrl.dtsi | 65 st,bank-name = "PIO0";
73 st,bank-name = "PIO1";
81 st,bank-name = "PIO2";
89 st,bank-name = "PIO3";
97 st,bank-name = "PIO4";
105 st,bank-name = "PIO40";
261 st,bank-name = "PIO5";
269 st,bank-name = "PIO6";
277 st,bank-name = "PIO7";
285 st,bank-name = "PIO8";
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| /arch/blackfin/mach-common/ |
| D | pm.c | 107 register u32 way, bank, subbank, set; in flushinv_all_dcache() local
111 for (bank = 0; bank < 2; ++bank) { in flushinv_all_dcache()
112 if (!(dmem_ctl & (1 << (DMC1_P - bank)))) in flushinv_all_dcache()
121 bank << 23 | in flushinv_all_dcache()
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