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/arch/mips/alchemy/common/
Dusb.c97 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) in __au1300_usb_phyctl() argument
101 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
102 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
111 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
117 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
122 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) in __au1300_ohci_control() argument
127 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
130 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
133 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
136 __au1300_usb_phyctl(base, enable); /* power up the PHYs */ in __au1300_ohci_control()
[all …]
Dvss.c24 void __iomem *base = (void __iomem *)VSS_ADDR(block); in __enable_block() local
26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
29 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
33 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
35 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
37 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
39 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
42 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
45 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
48 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
[all …]
Dirq.c291 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_unmask() local
293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
301 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_unmask() local
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
311 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_mask() local
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
321 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_mask() local
[all …]
/arch/arm/plat-orion/
Dpcie.c55 u32 orion_pcie_dev_id(void __iomem *base) in orion_pcie_dev_id() argument
57 return readl(base + PCIE_DEV_ID_OFF) >> 16; in orion_pcie_dev_id()
60 u32 orion_pcie_rev(void __iomem *base) in orion_pcie_rev() argument
62 return readl(base + PCIE_DEV_REV_OFF) & 0xff; in orion_pcie_rev()
65 int orion_pcie_link_up(void __iomem *base) in orion_pcie_link_up() argument
67 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); in orion_pcie_link_up()
70 int __init orion_pcie_x4_mode(void __iomem *base) in orion_pcie_x4_mode() argument
72 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); in orion_pcie_x4_mode()
75 int orion_pcie_get_local_bus_nr(void __iomem *base) in orion_pcie_get_local_bus_nr() argument
77 u32 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_get_local_bus_nr()
[all …]
/arch/m68k/amiga/
Dcia.c51 unsigned char cia_set_irq(struct ciabase *base, unsigned char mask) in cia_set_irq() argument
55 old = (base->icr_data |= base->cia->icr); in cia_set_irq()
57 base->icr_data |= mask; in cia_set_irq()
59 base->icr_data &= ~mask; in cia_set_irq()
60 if (base->icr_data & base->icr_mask) in cia_set_irq()
61 amiga_custom.intreq = IF_SETCLR | base->int_mask; in cia_set_irq()
62 return old & base->icr_mask; in cia_set_irq()
69 unsigned char cia_able_irq(struct ciabase *base, unsigned char mask) in cia_able_irq() argument
73 old = base->icr_mask; in cia_able_irq()
74 base->icr_data |= base->cia->icr; in cia_able_irq()
[all …]
/arch/alpha/kernel/
Dpc873xx.c12 static unsigned int base, model; variable
17 return base; in pc873xx_get_base()
25 static unsigned char __init pc873xx_read(unsigned int base, int reg) in pc873xx_read() argument
27 outb(reg, base); in pc873xx_read()
28 return inb(base + 1); in pc873xx_read()
31 static void __init pc873xx_write(unsigned int base, int reg, unsigned char data) in pc873xx_write() argument
36 outb(reg, base); in pc873xx_write()
37 outb(data, base + 1); in pc873xx_write()
38 outb(data, base + 1); /* Must be written twice */ in pc873xx_write()
46 while ((base = pc873xx_probelist[index++])) { in pc873xx_probe()
[all …]
/arch/arm/mach-realview/include/mach/
Duncompress.h29 #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) argument
30 #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) argument
31 #define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) argument
32 #define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) argument
58 unsigned long base = get_uart_base(); in putc() local
60 while (AMBA_UART_FR(base) & (1 << 5)) in putc()
63 AMBA_UART_DR(base) = c; in putc()
68 unsigned long base = get_uart_base(); in flush() local
70 while (AMBA_UART_FR(base) & (1 << 3)) in flush()
/arch/powerpc/include/asm/
Dppc_asm.h78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) argument
79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) argument
80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) argument
81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) argument
83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) argument
84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) argument
85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ argument
86 SAVE_10GPRS(22, base)
87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ argument
88 REST_10GPRS(22, base)
[all …]
/arch/sparc/kernel/
Dkstack.h12 unsigned long base = (unsigned long) tp; in kstack_valid() local
18 if (sp >= (base + sizeof(struct thread_info)) && in kstack_valid()
19 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) in kstack_valid()
23 base = (unsigned long) hardirq_stack[tp->cpu]; in kstack_valid()
24 if (sp >= base && in kstack_valid()
25 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) in kstack_valid()
27 base = (unsigned long) softirq_stack[tp->cpu]; in kstack_valid()
28 if (sp >= base && in kstack_valid()
29 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) in kstack_valid()
38 unsigned long base = (unsigned long) tp; in kstack_is_trap_frame() local
[all …]
Dbtext.c22 static void draw_byte_32(unsigned char *bits, unsigned int *base, int rb);
23 static void draw_byte_16(unsigned char *bits, unsigned int *base, int rb);
24 static void draw_byte_8(unsigned char *bits, unsigned int *base, int rb);
89 unsigned char *base = dispDeviceBase; in calc_base() local
91 base += (x + dispDeviceRect[0]) * (dispDeviceDepth >> 3); in calc_base()
92 base += (y + dispDeviceRect[1]) * dispDeviceRowBytes; in calc_base()
93 return base; in calc_base()
98 unsigned int *base = (unsigned int *)calc_base(0, 0); in btext_clearscreen() local
105 unsigned int *ptr = base; in btext_clearscreen()
108 base += (dispDeviceRowBytes >> 2); in btext_clearscreen()
[all …]
/arch/arm/include/asm/
Dvfpmacros.h20 .macro VFPFLDMIA, base, tmp in toolkits()
22 LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15} in toolkits()
24 LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
31 ldcnel p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
32 addeq \base, \base, #32*4 @ step over unused register space
37 ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
38 addne \base, \base, #32*4 @ step over unused register space
44 .macro VFPFSTMIA, base, tmp
46 STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
48 STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
[all …]
Dcti.h49 void __iomem *base; member
66 void __iomem *base, int irq, int trig_out) in cti_init() argument
68 cti->base = base; in cti_init()
86 void __iomem *base = cti->base; in cti_map_trigger() local
89 val = __raw_readl(base + CTIINEN + trig_in * 4); in cti_map_trigger()
91 __raw_writel(val, base + CTIINEN + trig_in * 4); in cti_map_trigger()
93 val = __raw_readl(base + CTIOUTEN + trig_out * 4); in cti_map_trigger()
95 __raw_writel(val, base + CTIOUTEN + trig_out * 4); in cti_map_trigger()
106 __raw_writel(0x1, cti->base + CTICONTROL); in cti_enable()
117 __raw_writel(0, cti->base + CTICONTROL); in cti_disable()
[all …]
/arch/mips/ath25/
Dearly_printk.c17 static inline void prom_uart_wr(void __iomem *base, unsigned reg, in prom_uart_wr() argument
20 __raw_writel(ch, base + 4 * reg); in prom_uart_wr()
23 static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) in prom_uart_rr() argument
25 return __raw_readl(base + 4 * reg); in prom_uart_rr()
30 static void __iomem *base; in prom_putchar() local
32 if (unlikely(base == NULL)) { in prom_putchar()
34 base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE)); in prom_putchar()
36 base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE)); in prom_putchar()
39 while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) in prom_putchar()
41 prom_uart_wr(base, UART_TX, ch); in prom_putchar()
[all …]
/arch/x86/mm/
Damdtopology.c99 u64 base, limit; in amd_numa_init() local
101 base = read_pci_config(0, nb, 1, 0x40 + i*8); in amd_numa_init()
105 if ((base & 3) == 0) { in amd_numa_init()
112 base, limit); in amd_numa_init()
118 i, base); in amd_numa_init()
121 if ((base >> 8) & 3 || (limit >> 8) & 3) { in amd_numa_init()
123 nodeid, (base >> 8) & 3, (limit >> 8) & 3); in amd_numa_init()
138 if (limit <= base) in amd_numa_init()
141 base >>= 16; in amd_numa_init()
142 base <<= 24; in amd_numa_init()
[all …]
/arch/arm/mach-mmp/
Ddevices.c81 static unsigned int u2o_get(void __iomem *base, unsigned int offset) in u2o_get() argument
83 return readl_relaxed(base + offset); in u2o_get()
86 static void u2o_set(void __iomem *base, unsigned int offset, in u2o_set() argument
91 reg = readl_relaxed(base + offset); in u2o_set()
93 writel_relaxed(reg, base + offset); in u2o_set()
94 readl_relaxed(base + offset); in u2o_set()
97 static void u2o_clear(void __iomem *base, unsigned int offset, in u2o_clear() argument
102 reg = readl_relaxed(base + offset); in u2o_clear()
104 writel_relaxed(reg, base + offset); in u2o_clear()
105 readl_relaxed(base + offset); in u2o_clear()
[all …]
/arch/arm/mm/
Dcache-l2x0.c74 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) in l2c_write_sec() argument
76 if (val == readl_relaxed(base + reg)) in l2c_write_sec()
81 writel_relaxed(val, base + reg); in l2c_write_sec()
89 static inline void l2c_set_debug(void __iomem *base, unsigned long val) in l2c_set_debug() argument
91 l2c_write_sec(val, base, L2X0_DEBUG_CTRL); in l2c_set_debug()
100 static inline void l2c_unlock(void __iomem *base, unsigned num) in l2c_unlock() argument
105 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + in l2c_unlock()
107 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + in l2c_unlock()
112 static void l2c_configure(void __iomem *base) in l2c_configure() argument
114 l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); in l2c_configure()
[all …]
/arch/arm/plat-samsung/
Dpm-gpio.c35 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_1bit_save()
36 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_1bit_save()
41 void __iomem *base = chip->base; in samsung_gpio_pm_1bit_resume() local
42 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
43 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
54 __raw_writel(gpcon, base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
58 __raw_writel(gps_gpdat, base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
59 __raw_writel(gps_gpcon, base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
72 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_2bit_save()
73 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_2bit_save()
[all …]
/arch/arm/mach-shmobile/
Dsetup-rcar-gen2.c56 void __iomem *base; in rcar_gen2_timer_init() local
108 base = ioremap(0xe6080000, PAGE_SIZE); in rcar_gen2_timer_init()
117 if ((ioread32(base + CNTCR) & 1) == 0 || in rcar_gen2_timer_init()
118 ioread32(base + CNTFID0) != freq) { in rcar_gen2_timer_init()
120 iowrite32(freq, base + CNTFID0); in rcar_gen2_timer_init()
124 iowrite32(1, base + CNTCR); in rcar_gen2_timer_init()
127 iounmap(base); in rcar_gen2_timer_init()
136 u64 base, size; member
160 u64 base, size; in rcar_gen2_scan_mem() local
162 base = dt_mem_next_cell(dt_root_addr_cells, &reg); in rcar_gen2_scan_mem()
[all …]
/arch/mips/include/asm/netlogic/
Dhaldefs.h46 nlm_read_reg(uint64_t base, uint32_t reg) in nlm_read_reg() argument
48 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; in nlm_read_reg()
54 nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) in nlm_write_reg() argument
56 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; in nlm_write_reg()
71 nlm_read_reg64(uint64_t base, uint32_t reg) in nlm_read_reg64() argument
73 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); in nlm_read_reg64()
98 nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) in nlm_write_reg64() argument
100 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); in nlm_write_reg64()
129 nlm_read_reg_xkphys(uint64_t base, uint32_t reg) in nlm_read_reg_xkphys() argument
131 return nlm_read_reg(base, reg); in nlm_read_reg_xkphys()
[all …]
/arch/arm/common/
Dscoop.c36 void __iomem *base; member
48 iowrite16(0x0100, sdev->base + SCOOP_MCR); /* 00 */ in reset_scoop()
49 iowrite16(0x0000, sdev->base + SCOOP_CDR); /* 04 */ in reset_scoop()
50 iowrite16(0x0000, sdev->base + SCOOP_CCR); /* 10 */ in reset_scoop()
51 iowrite16(0x0000, sdev->base + SCOOP_IMR); /* 18 */ in reset_scoop()
52 iowrite16(0x00FF, sdev->base + SCOOP_IRM); /* 14 */ in reset_scoop()
53 iowrite16(0x0000, sdev->base + SCOOP_ISR); /* 1C */ in reset_scoop()
54 iowrite16(0x0000, sdev->base + SCOOP_IRM); in reset_scoop()
62 gpwr = ioread16(sdev->base + SCOOP_GPWR); in __scoop_gpio_set()
67 iowrite16(gpwr, sdev->base + SCOOP_GPWR); in __scoop_gpio_set()
[all …]
/arch/mips/include/asm/netlogic/xlp-hal/
Duart.h103 nlm_uart_set_baudrate(uint64_t base, int baud) in nlm_uart_set_baudrate() argument
107 lcr = nlm_read_uart_reg(base, UART_LINE_CTL); in nlm_uart_set_baudrate()
110 nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7)); in nlm_uart_set_baudrate()
111 nlm_write_uart_reg(base, UART_DIVISOR0, in nlm_uart_set_baudrate()
113 nlm_write_uart_reg(base, UART_DIVISOR1, in nlm_uart_set_baudrate()
117 nlm_write_uart_reg(base, UART_LINE_CTL, lcr); in nlm_uart_set_baudrate()
121 nlm_uart_outbyte(uint64_t base, char c) in nlm_uart_outbyte() argument
126 lsr = nlm_read_uart_reg(base, UART_LINE_STS); in nlm_uart_outbyte()
131 nlm_write_uart_reg(base, UART_TX_DATA, (int)c); in nlm_uart_outbyte()
135 nlm_uart_inbyte(uint64_t base) in nlm_uart_inbyte() argument
[all …]
Dpic.h228 nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, in nlm_9xx_pic_write_irt() argument
238 nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val); in nlm_9xx_pic_write_irt()
242 nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, in nlm_pic_write_irt() argument
252 nlm_write_pic_reg(base, PIC_IRT(irt_num), val); in nlm_pic_write_irt()
256 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, in nlm_pic_write_irt_direct() argument
260 nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec, in nlm_pic_write_irt_direct()
263 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, in nlm_pic_write_irt_direct()
269 nlm_pic_read_timer(uint64_t base, int timer) in nlm_pic_read_timer() argument
271 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); in nlm_pic_read_timer()
275 nlm_pic_read_timer32(uint64_t base, int timer) in nlm_pic_read_timer32() argument
[all …]
/arch/arm/plat-orion/include/plat/
Dpcie.h16 u32 orion_pcie_dev_id(void __iomem *base);
17 u32 orion_pcie_rev(void __iomem *base);
18 int orion_pcie_link_up(void __iomem *base);
19 int orion_pcie_x4_mode(void __iomem *base);
20 int orion_pcie_get_local_bus_nr(void __iomem *base);
21 void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
22 void orion_pcie_reset(void __iomem *base);
23 void orion_pcie_setup(void __iomem *base);
24 int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
26 int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
[all …]
/arch/arm/mach-gemini/
Dgpio.c48 static void _set_gpio_irqenable(void __iomem *base, unsigned int index, in _set_gpio_irqenable() argument
53 reg = __raw_readl(base + GPIO_INT_EN); in _set_gpio_irqenable()
55 __raw_writel(reg, base + GPIO_INT_EN); in _set_gpio_irqenable()
61 void __iomem *base = GPIO_BASE(gpio / 32); in gpio_ack_irq() local
63 __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR); in gpio_ack_irq()
69 void __iomem *base = GPIO_BASE(gpio / 32); in gpio_mask_irq() local
71 _set_gpio_irqenable(base, gpio % 32, 0); in gpio_mask_irq()
77 void __iomem *base = GPIO_BASE(gpio / 32); in gpio_unmask_irq() local
79 _set_gpio_irqenable(base, gpio % 32, 1); in gpio_unmask_irq()
86 void __iomem *base = GPIO_BASE(gpio / 32); in gpio_set_irq_type() local
[all …]
/arch/arm/mach-netx/include/mach/
Duncompress.h45 unsigned long base; in putc() local
48 base = UART1_BASE; in putc()
50 base = UART2_BASE; in putc()
54 while (REG(base + UART_FR) & FR_TXFF); in putc()
55 REG(base + UART_DR) = c; in putc()
60 unsigned long base; in flush() local
63 base = UART1_BASE; in flush()
65 base = UART2_BASE; in flush()
69 while (REG(base + UART_FR) & FR_BUSY); in flush()

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