Searched refs:bcpu (Results 1 – 3 of 3) sorted by relevance
168 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; in uv_rtc_allocate_timers() local186 head->cpu[bcpu].lcpu = cpu; in uv_rtc_allocate_timers()187 head->cpu[bcpu].expires = ULLONG_MAX; in uv_rtc_allocate_timers()197 int c, bcpu = -1; in uv_rtc_find_next_timer() local203 bcpu = c; in uv_rtc_find_next_timer()207 if (bcpu >= 0) { in uv_rtc_find_next_timer()208 head->next_cpu = bcpu; in uv_rtc_find_next_timer()209 c = head->cpu[bcpu].lcpu; in uv_rtc_find_next_timer()229 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; in uv_rtc_set_timer() local230 u64 *t = &head->cpu[bcpu].expires; in uv_rtc_set_timer()[all …]
64 register int bcpu = boot_cpuid; in titan_update_irq_hw() local78 if (bcpu == 0) mask0 |= isa_enable; in titan_update_irq_hw()79 else if (bcpu == 1) mask1 |= isa_enable; in titan_update_irq_hw()80 else if (bcpu == 2) mask2 |= isa_enable; in titan_update_irq_hw()104 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()105 else if (bcpu == 2) dimB = &cchip->dim2.csr; in titan_update_irq_hw()106 else if (bcpu == 3) dimB = &cchip->dim3.csr; in titan_update_irq_hw()
51 register int bcpu = boot_cpuid; in tsunami_update_irq_hw() local63 if (bcpu == 0) mask0 |= isa_enable; in tsunami_update_irq_hw()64 else if (bcpu == 1) mask1 |= isa_enable; in tsunami_update_irq_hw()65 else if (bcpu == 2) mask2 |= isa_enable; in tsunami_update_irq_hw()88 if (bcpu == 0) dimB = &cchip->dim0.csr; in tsunami_update_irq_hw()89 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()90 else if (bcpu == 2) dimB = &cchip->dim2.csr; in tsunami_update_irq_hw()