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Searched refs:c2 (Results 1 – 25 of 60) sorted by relevance

123

/arch/arm/kvm/
Dinit.S75 mcrr p15, 4, rr_lo_hi(r2, r3), c2
79 mrc p15, 4, r0, c2, c0, 2 @ HTCR
82 mrc p15, 0, r1, c2, c0, 2 @ TTBCR
85 mcr p15, 4, r0, c2, c0, 2 @ HTCR
87 mrc p15, 4, r1, c2, c1, 2 @ VTCR
93 mcr p15, 4, r1, c2, c1, 2 @ VTCR
97 mrc p15, 0, r0, c10, c2, 0
98 mcr p15, 4, r0, c10, c2, 0
99 mrc p15, 0, r0, c10, c2, 1
100 mcr p15, 4, r0, c10, c2, 1
Dinterrupts.S55 mcrr p15, 6, rr_lo_hi(r2, r3), c2 @ Write VTTBR
62 mcrr p15, 6, r2, r3, c2 @ Back to VMID #0
168 mcrr p15, 6, r2, r3, c2 @ Write VTTBR
282 mrrc p15, 6, r0, r1, c2 @ Read VTTBR
289 mrc p15, 4, r2, c5, c2, 0 @ HSR
295 mrc p15, 4, r2, c5, c2, 0 @ HSR
371 mrrc p15, 6, r0, r2, c2
438 mrc p15, 4, r1, c5, c2, 0 @ HSR
Dinterrupts_head.S253 mrc p15, 0, r4, c2, c0, 2 @ TTBCR
255 mrrc p15, 0, r6, r7, c2 @ TTBR 0
256 mrrc p15, 1, r8, r9, c2 @ TTBR 1
257 mrc p15, 0, r10, c10, c2, 0 @ PRRR
258 mrc p15, 0, r11, c10, c2, 1 @ NMRR
390 mcr p15, 0, r4, c2, c0, 2 @ TTBCR
392 mcrr p15, 0, r6, r7, c2 @ TTBR 0
393 mcrr p15, 1, r8, r9, c2 @ TTBR 1
394 mcr p15, 0, r10, c10, c2, 0 @ PRRR
395 mcr p15, 0, r11, c10, c2, 1 @ NMRR
/arch/mips/include/asm/sibyte/
Dboard.h42 #define setleds(t0, t1, c0, c1, c2, c3) \
48 li t1, c2; \
53 #define setleds(t0, t1, c0, c1, c2, c3)
/arch/arm/include/asm/hardware/
Dcp14.h62 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
67 #define RCP14_DBGBVR2() MRC14(0, c0, c2, 4)
83 #define RCP14_DBGBCR2() MRC14(0, c0, c2, 5)
99 #define RCP14_DBGWVR2() MRC14(0, c0, c2, 6)
115 #define RCP14_DBGWCR2() MRC14(0, c0, c2, 7)
132 #define RCP14_DBGBXVR2() MRC14(0, c1, c2, 1)
147 #define RCP14_DBGOSSRR() MRC14(0, c1, c2, 4)
151 #define RCP14_DBGDSAR() MRC14(0, c2, c0, 0)
158 #define RCP14_DBGDEVID() MRC14(0, c7, c2, 7)
167 #define WCP14_DBGDSCRext(val) MCR14(val, 0, c0, c2, 2)
[all …]
/arch/x86/boot/
Dstring.c54 unsigned char c1, c2; in strncmp() local
58 c2 = *ct++; in strncmp()
59 if (c1 != c2) in strncmp()
60 return c1 < c2 ? -1 : 1; in strncmp()
/arch/arm/mm/
Dproc-v7-3level.S62 mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0
132 mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
144 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
148 mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1
Dpv-fixup-asm.S66 mrrc p15, 0, r4, r5, c2 @ read TTBR0
69 mcrr p15, 0, r4, r5, c2 @ write back TTBR0
70 mrrc p15, 1, r4, r5, c2 @ read TTBR1
73 mcrr p15, 1, r4, r5, c2 @ write back TTBR1
Dproc-v6.S107 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
145 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
167 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
168 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
169 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
218 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
Dproc-v7-2level.S59 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
148 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
153 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
Dproc-v7.S137 mrrc p15, 1, r5, r7, c2 @ TTB 1
139 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
141 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
162 mcrr p15, 0, r1, ip, c2 @ TTB 0
163 mcrr p15, 1, r5, r7, c2 @ TTB 1
167 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
168 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
170 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
173 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
174 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
[all …]
Dproc-sa1100.S56 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
151 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
194 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
Dproc-sa110.S48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
140 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
Dproc-xscale.S72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
477 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
554 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
Dproc-arm940.S308 mcr p15, 0, r3, c6, c2, 0 @ set area 2, ROM/FLASH
309 mcr p15, 0, r3, c6, c2, 1
312 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
313 mcr p15, 0, r0, c2, c0, 1
Dproc-arm740.S98 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
101 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
Dproc-arm946.S353 mcr p15, 0, r3, c6, c2, 0
356 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
357 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
/arch/arm/boot/compressed/
Dstring.c92 unsigned char c1, c2; in strcmp() local
97 c2 = *ct++; in strcmp()
98 res = c1 - c2; in strcmp()
/arch/arm/mach-iop13xx/include/mach/
Dentry-macro.S30 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
32 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
/arch/m68k/include/asm/
Dpage_mm.h78 m68k_fixup(%c2, 1b+2) in ___pa()
89 m68k_fixup(%c2, 1b+2) in __va()
/arch/unicore32/kernel/
Dhibernate_asm.S32 movc p0.c2, r0, #0
65 movc p0.c2, r0, #0
Dsleep.S25 movc r4, p0.c2, #0 @ translation table base addr
175 movc p0.c2, r4, #0 @ translation table base addr
/arch/powerpc/platforms/86xx/
Dmpc8610_hpcd.c150 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \ argument
154 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
/arch/powerpc/crypto/
Daes-tab-4k.S54 .long R(75, b7, b7, c2), R(e1, fd, fd, 1c)
122 .long R(9f, c2, c2, 5d), R(bd, d3, d3, 6e)
146 .long R(c2, 61, 61, a3), R(6a, 35, 35, 5f)
185 .long R(75, c2, 89, 6a), R(f4, 8e, 79, 78)
197 .long R(b2, eb, 28, 07), R(2f, b5, c2, 03)
255 .long R(f6, 8d, 13, c2), R(90, d8, b8, e8)
290 .long R(38, 24, 34, 2c), R(c2, a3, 40, 5f)
/arch/arm/kernel/
Diwmmxt.S96 mrc p15, 0, r2, c2, c0, 0
222 mrc p15, 0, r2, c2, c0, 0
232 mrc p15, 0, r2, c2, c0, 0
344 mrc p15, 0, r1, c2, c0, 0

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