Searched refs:cbr (Results 1 – 14 of 14) sorted by relevance
| /arch/mips/include/asm/ |
| D | bmips.h | 127 void __iomem *cbr = BMIPS_GET_CBR(); in bmips_post_dma_flush() local
136 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_post_dma_flush()
137 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); in bmips_post_dma_flush()
138 __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_post_dma_flush()
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| /arch/mips/kernel/ |
| D | smp-bmips.c | 499 void __iomem *cbr = BMIPS_GET_CBR(); in bmips_set_reset_vec() local
502 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); in bmips_set_reset_vec()
506 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); in bmips_set_reset_vec()
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| /arch/avr32/mach-at32ap/ |
| D | pm-at32ap700x.S | 60 cbr r9, TIF_CPU_GOING_TO_SLEEP
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| /arch/m32r/platforms/oaks32r/ |
| D | dot.gdbinit.nommu | 82 printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
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| /arch/m32r/platforms/mappi3/ |
| D | dot.gdbinit | 140 printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
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| /arch/m32r/platforms/mappi2/ |
| D | dot.gdbinit.vdec2 | 151 printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
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| /arch/m32r/platforms/m32700ut/ |
| D | dot.gdbinit_400MHz_32MB | 152 printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
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| D | dot.gdbinit_300MHz_32MB | 152 printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
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| D | dot.gdbinit_200MHz_16MB | 152 printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
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| /arch/m32r/platforms/mappi/ |
| D | dot.gdbinit.nommu | 168 printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
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| D | dot.gdbinit | 168 printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
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| D | dot.gdbinit.smp | 236 printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
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| /arch/m32r/platforms/opsput/ |
| D | dot.gdbinit | 177 printf "PSW[%08lx] CBR[%08lx] SPI[%08lx] SPU[%08lx]\n",$psw,$cbr,$spi,$spu
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| /arch/avr32/kernel/ |
| D | entry-avr32b.S | 577 cbr r8, SYSREG_M0_OFFSET
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