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/arch/mips/pci/
Dpci-octeon.c369 union cvmx_pci_cfg56 cfg56; in octeon_pci_initialize() local
535 cfg56.u32 = 0; in octeon_pci_initialize()
536 cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */ in octeon_pci_initialize()
537 cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */ in octeon_pci_initialize()
538 cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */ in octeon_pci_initialize()
539 cfg56.s.roe = 1; /* Relaxed Ordering Enable */ in octeon_pci_initialize()
540 cfg56.s.mmbc = 1; /* Maximum Memory Byte Count in octeon_pci_initialize()
542 cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1 in octeon_pci_initialize()
545 octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32); in octeon_pci_initialize()