Searched refs:clk_rst (Results 1 – 4 of 4) sorted by relevance
| /arch/arm/mach-mmp/ |
| D | clock-mmp2.c | 49 uint32_t clk_rst; in sdhc_clk_enable() local
51 clk_rst = __raw_readl(clk->clk_rst); in sdhc_clk_enable()
52 clk_rst |= clk->enable_val; in sdhc_clk_enable()
53 __raw_writel(clk_rst, clk->clk_rst); in sdhc_clk_enable()
58 uint32_t clk_rst; in sdhc_clk_disable() local
60 clk_rst = __raw_readl(clk->clk_rst); in sdhc_clk_disable()
61 clk_rst &= ~clk->enable_val; in sdhc_clk_disable()
62 __raw_writel(clk_rst, clk->clk_rst); in sdhc_clk_disable()
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| D | clock.c | 21 uint32_t clk_rst; in apbc_clk_enable() local
23 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel); in apbc_clk_enable()
24 __raw_writel(clk_rst, clk->clk_rst); in apbc_clk_enable()
29 __raw_writel(0, clk->clk_rst); in apbc_clk_disable()
39 __raw_writel(clk->enable_val, clk->clk_rst); in apmu_clk_enable()
44 __raw_writel(0, clk->clk_rst); in apmu_clk_disable()
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| D | clock.h | 21 void __iomem *clk_rst; /* clock reset control register */ member
33 .clk_rst = APBC_##_reg, \
41 .clk_rst = APBC_##_reg, \
49 .clk_rst = APMU_##_reg, \
57 .clk_rst = APMU_##_reg, \
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| D | mmp2.c | 125 unsigned long clk_rst; in mmp2_timer_init() local
133 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); in mmp2_timer_init()
134 __raw_writel(clk_rst, APBC_TIMERS); in mmp2_timer_init()
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