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Searched refs:cpsr (Results 1 – 25 of 26) sorted by relevance

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/arch/arm64/kvm/
Demulate.c70 unsigned long cpsr; in kvm_condition_valid32() local
83 cpsr = *vcpu_cpsr(vcpu); in kvm_condition_valid32()
89 it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3); in kvm_condition_valid32()
99 cpsr_cond = cpsr >> 28; in kvm_condition_valid32()
120 unsigned long cpsr = *vcpu_cpsr(vcpu); in kvm_adjust_itstate() local
121 bool is_arm = !(cpsr & COMPAT_PSR_T_BIT); in kvm_adjust_itstate()
123 BUG_ON(is_arm && (cpsr & COMPAT_PSR_IT_MASK)); in kvm_adjust_itstate()
125 if (!(cpsr & COMPAT_PSR_IT_MASK)) in kvm_adjust_itstate()
128 cond = (cpsr & 0xe000) >> 13; in kvm_adjust_itstate()
129 itbits = (cpsr & 0x1c00) >> (10 - 2); in kvm_adjust_itstate()
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Dinject_fault.c34 unsigned long cpsr; in prepare_fault32() local
40 cpsr = mode | COMPAT_PSR_I_BIT; in prepare_fault32()
43 cpsr |= COMPAT_PSR_T_BIT; in prepare_fault32()
45 cpsr |= COMPAT_PSR_E_BIT; in prepare_fault32()
47 *vcpu_cpsr(vcpu) = cpsr; in prepare_fault32()
102 unsigned long cpsr = *vcpu_cpsr(vcpu); in inject_abt64() local
108 *vcpu_spsr(vcpu) = cpsr; in inject_abt64()
127 if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t) in inject_abt64()
140 unsigned long cpsr = *vcpu_cpsr(vcpu); in inject_undef64() local
143 *vcpu_spsr(vcpu) = cpsr; in inject_undef64()
/arch/arm/probes/
Ddecode.c87 static unsigned long __kprobes __check_eq(unsigned long cpsr) in __check_eq() argument
89 return cpsr & PSR_Z_BIT; in __check_eq()
92 static unsigned long __kprobes __check_ne(unsigned long cpsr) in __check_ne() argument
94 return (~cpsr) & PSR_Z_BIT; in __check_ne()
97 static unsigned long __kprobes __check_cs(unsigned long cpsr) in __check_cs() argument
99 return cpsr & PSR_C_BIT; in __check_cs()
102 static unsigned long __kprobes __check_cc(unsigned long cpsr) in __check_cc() argument
104 return (~cpsr) & PSR_C_BIT; in __check_cc()
107 static unsigned long __kprobes __check_mi(unsigned long cpsr) in __check_mi() argument
109 return cpsr & PSR_N_BIT; in __check_mi()
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Ddecode.h52 static inline unsigned long it_advance(unsigned long cpsr) in it_advance() argument
54 if ((cpsr & 0x06000400) == 0) { in it_advance()
56 cpsr &= ~PSR_IT_MASK; in it_advance()
60 unsigned long it = cpsr & mask; in it_advance()
64 cpsr &= ~mask; in it_advance()
65 cpsr |= it; in it_advance()
67 return cpsr; in it_advance()
72 long cpsr = regs->ARM_cpsr; in bx_write_pc() local
74 cpsr |= PSR_T_BIT; in bx_write_pc()
77 cpsr &= ~PSR_T_BIT; in bx_write_pc()
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Ddecode-thumb.h23 #define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000) argument
30 #define current_cond(cpsr) ((cpsr >> 12) & 0xf) argument
Ddecode-thumb.c839 static unsigned long __kprobes thumb_check_cc(unsigned long cpsr) in thumb_check_cc() argument
841 if (unlikely(in_it_block(cpsr))) in thumb_check_cc()
842 return probes_condition_checks[current_cond(cpsr)](cpsr); in thumb_check_cc()
/arch/arm/kvm/
Demulate.c171 unsigned long cpsr, cond, insn; in kvm_condition_valid() local
184 cpsr = *vcpu_cpsr(vcpu); in kvm_condition_valid()
193 it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3); in kvm_condition_valid()
205 return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL; in kvm_condition_valid()
221 unsigned long cpsr = *vcpu_cpsr(vcpu); in kvm_adjust_itstate() local
222 bool is_arm = !(cpsr & PSR_T_BIT); in kvm_adjust_itstate()
224 BUG_ON(is_arm && (cpsr & PSR_IT_MASK)); in kvm_adjust_itstate()
226 if (!(cpsr & PSR_IT_MASK)) in kvm_adjust_itstate()
229 cond = (cpsr & 0xe000) >> 13; in kvm_adjust_itstate()
230 itbits = (cpsr & 0x1c00) >> (10 - 2); in kvm_adjust_itstate()
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Dtrace.h117 unsigned long cpsr),
118 TP_ARGS(vcpu_pc, instr, cpsr),
123 __field( unsigned long, cpsr )
129 __entry->cpsr = cpsr;
133 __entry->vcpu_pc, __entry->instr, __entry->cpsr)
/arch/arm/probes/kprobes/
Dactions-arm.c178 unsigned long cpsr = regs->ARM_cpsr; in emulate_rd12rn16rm0rs8_rwflags() local
184 : "=r" (rdv), [cpsr] "=r" (cpsr) in emulate_rd12rn16rm0rs8_rwflags()
186 "1" (cpsr), [fn] "r" (asi->insn_fn) in emulate_rd12rn16rm0rs8_rwflags()
194 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); in emulate_rd12rn16rm0rs8_rwflags()
208 unsigned long cpsr = regs->ARM_cpsr; in emulate_rd12rn16rm0_rwflags_nopc() local
214 : "=r" (rdv), [cpsr] "=r" (cpsr) in emulate_rd12rn16rm0_rwflags_nopc()
216 "1" (cpsr), [fn] "r" (asi->insn_fn) in emulate_rd12rn16rm0_rwflags_nopc()
221 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); in emulate_rd12rn16rm0_rwflags_nopc()
238 unsigned long cpsr = regs->ARM_cpsr; in emulate_rd16rn12rm0rs8_rwflags_nopc() local
244 : "=r" (rdv), [cpsr] "=r" (cpsr) in emulate_rd16rn12rm0rs8_rwflags_nopc()
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Dactions-thumb.c224 unsigned long cpsr = regs->ARM_cpsr; in t32_emulate_rd8rn16rm0_rwflags() local
230 : "=r" (rdv), [cpsr] "=r" (cpsr) in t32_emulate_rd8rn16rm0_rwflags()
232 "1" (cpsr), [fn] "r" (asi->insn_fn) in t32_emulate_rd8rn16rm0_rwflags()
237 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); in t32_emulate_rd8rn16rm0_rwflags()
391 unsigned long cpsr = regs->ARM_cpsr; in t16_simulate_it() local
392 cpsr &= ~PSR_IT_MASK; in t16_simulate_it()
393 cpsr |= (insn & 0xfc) << 8; in t16_simulate_it()
394 cpsr |= (insn & 0x03) << 25; in t16_simulate_it()
395 regs->ARM_cpsr = cpsr; in t16_simulate_it()
478 unsigned long cpsr = t16_emulate_loregs(insn, asi, regs); in t16_emulate_loregs_noitrwflags() local
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Dtest-core.c1068 static unsigned long test_check_cc(int cc, unsigned long cpsr) in test_check_cc() argument
1070 int ret = arm_check_condition(cc << 28, cpsr); in test_check_cc()
1081 unsigned long cpsr; in test_context_cpsr() local
1086 cpsr = (scenario & 0xf) << 28; /* N,Z,C,V flags */ in test_context_cpsr()
1087 cpsr |= (scenario & 0xf) << 16; /* GE flags */ in test_context_cpsr()
1088 cpsr |= (scenario & 0x1) << 27; /* Toggle Q flag */ in test_context_cpsr()
1094 probe_should_run = test_check_cc(cc, cpsr) != 0; in test_context_cpsr()
1102 probe_should_run = test_check_cc(cc, cpsr) != 0; in test_context_cpsr()
1122 cpsr |= cond_base << 13; /* ITSTATE<7:5> */ in test_context_cpsr()
1123 cpsr |= (mask & 0x1) << 12; /* ITSTATE<4> */ in test_context_cpsr()
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Dcore.c528 long cpsr; in setjmp_pre_handler() local
534 cpsr = regs->ARM_cpsr | PSR_I_BIT; in setjmp_pre_handler()
538 cpsr |= PSR_T_BIT; in setjmp_pre_handler()
540 cpsr &= ~PSR_T_BIT; in setjmp_pre_handler()
542 regs->ARM_cpsr = cpsr; in setjmp_pre_handler()
/arch/arm/kernel/
Dfiqasm.S27 mrs r1, cpsr
40 mrs r1, cpsr
Dsignal.c337 unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT); in setup_return() local
339 cpsr |= PSR_ENDSTATE; in setup_return()
345 cpsr = (cpsr & ~MODE_MASK) | USR_MODE; in setup_return()
366 cpsr &= ~PSR_IT_MASK; in setup_return()
369 cpsr |= PSR_T_BIT; in setup_return()
371 cpsr &= ~PSR_T_BIT; in setup_return()
392 if (cpsr & MODE32_BIT) { in setup_return()
420 regs->ARM_cpsr = cpsr; in setup_return()
Dhyp-stub.S41 mrs \reg1, cpsr
94 mrs r4, cpsr
Diwmmxt.S199 mrs ip, cpsr
251 mrs ip, cpsr
289 mrs ip, cpsr
356 mrs r2, cpsr
Dentry-header.S176 mrs \rtemp, cpsr
188 mrs \rtemp, cpsr
327 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
343 movs pc, lr @ return & move spsr_svc into cpsr
Dentry-armv.S293 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
1044 mrs r0, cpsr
Dptrace.c88 REG_OFFSET_NAME(cpsr),
/arch/arm/lib/
Decard.S17 mrs rt, cpsr; \
/arch/arm/mach-ep93xx/
Dcrunch-bits.S212 mrs ip, cpsr
258 mrs ip, cpsr
291 mrs ip, cpsr
/arch/arm/include/asm/
Dassembler.h156 mrs \oldcpsr, cpsr
162 mrs \oldcpsr, cpsr
340 mrs \reg , cpsr
/arch/arm/mm/
Dproc-feroceon.S261 mrs r2, cpsr
302 mrs r2, cpsr
338 mrs r2, cpsr
369 mrs r2, cpsr
Dcache-v6.S41 mrs r1, cpsr
Dproc-arm926.S107 mrs r3, cpsr @ Disable FIQs while Icache

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