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1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: support@caviumnetworks.com
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_CIU_DEFS_H__
29 #define __CVMX_CIU_DEFS_H__
30 
31 #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
32 #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
33 #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
34 #define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8)
35 #define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8)
36 #define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8)
37 #define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8)
38 #define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8)
39 #define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8)
40 #define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8)
41 #define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8)
42 #define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8)
43 #define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8)
44 #define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8)
45 #define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8)
46 #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
47 #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
48 #define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
49 #define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16)
50 #define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16)
51 #define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16)
52 #define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16)
53 #define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16)
54 #define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16)
55 #define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16)
56 #define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16)
57 #define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16)
58 #define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16)
59 #define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16)
60 #define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16)
61 #define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8)
62 #define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8)
63 #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
64 #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
CVMX_CIU_MBOX_CLRX(unsigned long offset)65 static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
66 {
67 	switch (cvmx_get_octeon_family()) {
68 	case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
69 		return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
70 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
71 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
72 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
73 		return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
74 	case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
75 	case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
76 		return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
77 	case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
78 	case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
79 		return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
80 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
81 		return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
82 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
83 		return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
84 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
85 		return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
86 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
87 		return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8;
88 	}
89 	return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
90 }
91 
CVMX_CIU_MBOX_SETX(unsigned long offset)92 static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
93 {
94 	switch (cvmx_get_octeon_family()) {
95 	case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
96 		return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
97 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
98 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
99 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
100 		return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
101 	case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
102 	case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
103 		return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
104 	case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
105 	case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
106 		return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
107 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
108 		return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
109 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
110 		return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
111 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
112 		return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
113 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
114 		return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8;
115 	}
116 	return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
117 }
118 
119 #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
120 #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
121 #define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
122 #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
CVMX_CIU_PP_POKEX(unsigned long offset)123 static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
124 {
125 	switch (cvmx_get_octeon_family()) {
126 	case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
127 		return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
128 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
129 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
130 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
131 		return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
132 	case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
133 	case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
134 		return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
135 	case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
136 	case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
137 		return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
138 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
139 		return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
140 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
141 		return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
142 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
143 		return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
144 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
145 		return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8;
146 	}
147 	return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
148 }
149 
150 #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
151 #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
152 #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
153 #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
154 #define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull))
155 #define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull))
156 #define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
157 #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
158 #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
159 #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
160 #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
161 #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
162 #define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull))
163 #define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
164 #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
165 #define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8)
166 #define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8)
167 #define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8)
168 #define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8)
169 #define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8)
170 #define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8)
171 #define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8)
172 #define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8)
173 #define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8)
174 #define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull))
CVMX_CIU_WDOGX(unsigned long offset)175 static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
176 {
177 	switch (cvmx_get_octeon_family()) {
178 	case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
179 		return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
180 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
181 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
182 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
183 		return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
184 	case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
185 	case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
186 		return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
187 	case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
188 	case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
189 		return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
190 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
191 		return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
192 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
193 		return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
194 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
195 		return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
196 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
197 		return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8;
198 	}
199 	return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
200 }
201 
202 union cvmx_ciu_bist {
203 	uint64_t u64;
204 	struct cvmx_ciu_bist_s {
205 #ifdef __BIG_ENDIAN_BITFIELD
206 		uint64_t reserved_7_63:57;
207 		uint64_t bist:7;
208 #else
209 		uint64_t bist:7;
210 		uint64_t reserved_7_63:57;
211 #endif
212 	} s;
213 	struct cvmx_ciu_bist_cn30xx {
214 #ifdef __BIG_ENDIAN_BITFIELD
215 		uint64_t reserved_4_63:60;
216 		uint64_t bist:4;
217 #else
218 		uint64_t bist:4;
219 		uint64_t reserved_4_63:60;
220 #endif
221 	} cn30xx;
222 	struct cvmx_ciu_bist_cn30xx cn31xx;
223 	struct cvmx_ciu_bist_cn30xx cn38xx;
224 	struct cvmx_ciu_bist_cn30xx cn38xxp2;
225 	struct cvmx_ciu_bist_cn50xx {
226 #ifdef __BIG_ENDIAN_BITFIELD
227 		uint64_t reserved_2_63:62;
228 		uint64_t bist:2;
229 #else
230 		uint64_t bist:2;
231 		uint64_t reserved_2_63:62;
232 #endif
233 	} cn50xx;
234 	struct cvmx_ciu_bist_cn52xx {
235 #ifdef __BIG_ENDIAN_BITFIELD
236 		uint64_t reserved_3_63:61;
237 		uint64_t bist:3;
238 #else
239 		uint64_t bist:3;
240 		uint64_t reserved_3_63:61;
241 #endif
242 	} cn52xx;
243 	struct cvmx_ciu_bist_cn52xx cn52xxp1;
244 	struct cvmx_ciu_bist_cn30xx cn56xx;
245 	struct cvmx_ciu_bist_cn30xx cn56xxp1;
246 	struct cvmx_ciu_bist_cn30xx cn58xx;
247 	struct cvmx_ciu_bist_cn30xx cn58xxp1;
248 	struct cvmx_ciu_bist_cn61xx {
249 #ifdef __BIG_ENDIAN_BITFIELD
250 		uint64_t reserved_6_63:58;
251 		uint64_t bist:6;
252 #else
253 		uint64_t bist:6;
254 		uint64_t reserved_6_63:58;
255 #endif
256 	} cn61xx;
257 	struct cvmx_ciu_bist_cn63xx {
258 #ifdef __BIG_ENDIAN_BITFIELD
259 		uint64_t reserved_5_63:59;
260 		uint64_t bist:5;
261 #else
262 		uint64_t bist:5;
263 		uint64_t reserved_5_63:59;
264 #endif
265 	} cn63xx;
266 	struct cvmx_ciu_bist_cn63xx cn63xxp1;
267 	struct cvmx_ciu_bist_cn61xx cn66xx;
268 	struct cvmx_ciu_bist_s cn68xx;
269 	struct cvmx_ciu_bist_s cn68xxp1;
270 	struct cvmx_ciu_bist_cn61xx cnf71xx;
271 };
272 
273 union cvmx_ciu_block_int {
274 	uint64_t u64;
275 	struct cvmx_ciu_block_int_s {
276 #ifdef __BIG_ENDIAN_BITFIELD
277 		uint64_t reserved_62_63:2;
278 		uint64_t srio3:1;
279 		uint64_t srio2:1;
280 		uint64_t reserved_43_59:17;
281 		uint64_t ptp:1;
282 		uint64_t dpi:1;
283 		uint64_t dfm:1;
284 		uint64_t reserved_34_39:6;
285 		uint64_t srio1:1;
286 		uint64_t srio0:1;
287 		uint64_t reserved_31_31:1;
288 		uint64_t iob:1;
289 		uint64_t reserved_29_29:1;
290 		uint64_t agl:1;
291 		uint64_t reserved_27_27:1;
292 		uint64_t pem1:1;
293 		uint64_t pem0:1;
294 		uint64_t reserved_24_24:1;
295 		uint64_t asxpcs1:1;
296 		uint64_t asxpcs0:1;
297 		uint64_t reserved_21_21:1;
298 		uint64_t pip:1;
299 		uint64_t reserved_18_19:2;
300 		uint64_t lmc0:1;
301 		uint64_t l2c:1;
302 		uint64_t reserved_15_15:1;
303 		uint64_t rad:1;
304 		uint64_t usb:1;
305 		uint64_t pow:1;
306 		uint64_t tim:1;
307 		uint64_t pko:1;
308 		uint64_t ipd:1;
309 		uint64_t reserved_8_8:1;
310 		uint64_t zip:1;
311 		uint64_t dfa:1;
312 		uint64_t fpa:1;
313 		uint64_t key:1;
314 		uint64_t sli:1;
315 		uint64_t gmx1:1;
316 		uint64_t gmx0:1;
317 		uint64_t mio:1;
318 #else
319 		uint64_t mio:1;
320 		uint64_t gmx0:1;
321 		uint64_t gmx1:1;
322 		uint64_t sli:1;
323 		uint64_t key:1;
324 		uint64_t fpa:1;
325 		uint64_t dfa:1;
326 		uint64_t zip:1;
327 		uint64_t reserved_8_8:1;
328 		uint64_t ipd:1;
329 		uint64_t pko:1;
330 		uint64_t tim:1;
331 		uint64_t pow:1;
332 		uint64_t usb:1;
333 		uint64_t rad:1;
334 		uint64_t reserved_15_15:1;
335 		uint64_t l2c:1;
336 		uint64_t lmc0:1;
337 		uint64_t reserved_18_19:2;
338 		uint64_t pip:1;
339 		uint64_t reserved_21_21:1;
340 		uint64_t asxpcs0:1;
341 		uint64_t asxpcs1:1;
342 		uint64_t reserved_24_24:1;
343 		uint64_t pem0:1;
344 		uint64_t pem1:1;
345 		uint64_t reserved_27_27:1;
346 		uint64_t agl:1;
347 		uint64_t reserved_29_29:1;
348 		uint64_t iob:1;
349 		uint64_t reserved_31_31:1;
350 		uint64_t srio0:1;
351 		uint64_t srio1:1;
352 		uint64_t reserved_34_39:6;
353 		uint64_t dfm:1;
354 		uint64_t dpi:1;
355 		uint64_t ptp:1;
356 		uint64_t reserved_43_59:17;
357 		uint64_t srio2:1;
358 		uint64_t srio3:1;
359 		uint64_t reserved_62_63:2;
360 #endif
361 	} s;
362 	struct cvmx_ciu_block_int_cn61xx {
363 #ifdef __BIG_ENDIAN_BITFIELD
364 		uint64_t reserved_43_63:21;
365 		uint64_t ptp:1;
366 		uint64_t dpi:1;
367 		uint64_t reserved_31_40:10;
368 		uint64_t iob:1;
369 		uint64_t reserved_29_29:1;
370 		uint64_t agl:1;
371 		uint64_t reserved_27_27:1;
372 		uint64_t pem1:1;
373 		uint64_t pem0:1;
374 		uint64_t reserved_24_24:1;
375 		uint64_t asxpcs1:1;
376 		uint64_t asxpcs0:1;
377 		uint64_t reserved_21_21:1;
378 		uint64_t pip:1;
379 		uint64_t reserved_18_19:2;
380 		uint64_t lmc0:1;
381 		uint64_t l2c:1;
382 		uint64_t reserved_15_15:1;
383 		uint64_t rad:1;
384 		uint64_t usb:1;
385 		uint64_t pow:1;
386 		uint64_t tim:1;
387 		uint64_t pko:1;
388 		uint64_t ipd:1;
389 		uint64_t reserved_8_8:1;
390 		uint64_t zip:1;
391 		uint64_t dfa:1;
392 		uint64_t fpa:1;
393 		uint64_t key:1;
394 		uint64_t sli:1;
395 		uint64_t gmx1:1;
396 		uint64_t gmx0:1;
397 		uint64_t mio:1;
398 #else
399 		uint64_t mio:1;
400 		uint64_t gmx0:1;
401 		uint64_t gmx1:1;
402 		uint64_t sli:1;
403 		uint64_t key:1;
404 		uint64_t fpa:1;
405 		uint64_t dfa:1;
406 		uint64_t zip:1;
407 		uint64_t reserved_8_8:1;
408 		uint64_t ipd:1;
409 		uint64_t pko:1;
410 		uint64_t tim:1;
411 		uint64_t pow:1;
412 		uint64_t usb:1;
413 		uint64_t rad:1;
414 		uint64_t reserved_15_15:1;
415 		uint64_t l2c:1;
416 		uint64_t lmc0:1;
417 		uint64_t reserved_18_19:2;
418 		uint64_t pip:1;
419 		uint64_t reserved_21_21:1;
420 		uint64_t asxpcs0:1;
421 		uint64_t asxpcs1:1;
422 		uint64_t reserved_24_24:1;
423 		uint64_t pem0:1;
424 		uint64_t pem1:1;
425 		uint64_t reserved_27_27:1;
426 		uint64_t agl:1;
427 		uint64_t reserved_29_29:1;
428 		uint64_t iob:1;
429 		uint64_t reserved_31_40:10;
430 		uint64_t dpi:1;
431 		uint64_t ptp:1;
432 		uint64_t reserved_43_63:21;
433 #endif
434 	} cn61xx;
435 	struct cvmx_ciu_block_int_cn63xx {
436 #ifdef __BIG_ENDIAN_BITFIELD
437 		uint64_t reserved_43_63:21;
438 		uint64_t ptp:1;
439 		uint64_t dpi:1;
440 		uint64_t dfm:1;
441 		uint64_t reserved_34_39:6;
442 		uint64_t srio1:1;
443 		uint64_t srio0:1;
444 		uint64_t reserved_31_31:1;
445 		uint64_t iob:1;
446 		uint64_t reserved_29_29:1;
447 		uint64_t agl:1;
448 		uint64_t reserved_27_27:1;
449 		uint64_t pem1:1;
450 		uint64_t pem0:1;
451 		uint64_t reserved_23_24:2;
452 		uint64_t asxpcs0:1;
453 		uint64_t reserved_21_21:1;
454 		uint64_t pip:1;
455 		uint64_t reserved_18_19:2;
456 		uint64_t lmc0:1;
457 		uint64_t l2c:1;
458 		uint64_t reserved_15_15:1;
459 		uint64_t rad:1;
460 		uint64_t usb:1;
461 		uint64_t pow:1;
462 		uint64_t tim:1;
463 		uint64_t pko:1;
464 		uint64_t ipd:1;
465 		uint64_t reserved_8_8:1;
466 		uint64_t zip:1;
467 		uint64_t dfa:1;
468 		uint64_t fpa:1;
469 		uint64_t key:1;
470 		uint64_t sli:1;
471 		uint64_t reserved_2_2:1;
472 		uint64_t gmx0:1;
473 		uint64_t mio:1;
474 #else
475 		uint64_t mio:1;
476 		uint64_t gmx0:1;
477 		uint64_t reserved_2_2:1;
478 		uint64_t sli:1;
479 		uint64_t key:1;
480 		uint64_t fpa:1;
481 		uint64_t dfa:1;
482 		uint64_t zip:1;
483 		uint64_t reserved_8_8:1;
484 		uint64_t ipd:1;
485 		uint64_t pko:1;
486 		uint64_t tim:1;
487 		uint64_t pow:1;
488 		uint64_t usb:1;
489 		uint64_t rad:1;
490 		uint64_t reserved_15_15:1;
491 		uint64_t l2c:1;
492 		uint64_t lmc0:1;
493 		uint64_t reserved_18_19:2;
494 		uint64_t pip:1;
495 		uint64_t reserved_21_21:1;
496 		uint64_t asxpcs0:1;
497 		uint64_t reserved_23_24:2;
498 		uint64_t pem0:1;
499 		uint64_t pem1:1;
500 		uint64_t reserved_27_27:1;
501 		uint64_t agl:1;
502 		uint64_t reserved_29_29:1;
503 		uint64_t iob:1;
504 		uint64_t reserved_31_31:1;
505 		uint64_t srio0:1;
506 		uint64_t srio1:1;
507 		uint64_t reserved_34_39:6;
508 		uint64_t dfm:1;
509 		uint64_t dpi:1;
510 		uint64_t ptp:1;
511 		uint64_t reserved_43_63:21;
512 #endif
513 	} cn63xx;
514 	struct cvmx_ciu_block_int_cn63xx cn63xxp1;
515 	struct cvmx_ciu_block_int_cn66xx {
516 #ifdef __BIG_ENDIAN_BITFIELD
517 		uint64_t reserved_62_63:2;
518 		uint64_t srio3:1;
519 		uint64_t srio2:1;
520 		uint64_t reserved_43_59:17;
521 		uint64_t ptp:1;
522 		uint64_t dpi:1;
523 		uint64_t dfm:1;
524 		uint64_t reserved_33_39:7;
525 		uint64_t srio0:1;
526 		uint64_t reserved_31_31:1;
527 		uint64_t iob:1;
528 		uint64_t reserved_29_29:1;
529 		uint64_t agl:1;
530 		uint64_t reserved_27_27:1;
531 		uint64_t pem1:1;
532 		uint64_t pem0:1;
533 		uint64_t reserved_24_24:1;
534 		uint64_t asxpcs1:1;
535 		uint64_t asxpcs0:1;
536 		uint64_t reserved_21_21:1;
537 		uint64_t pip:1;
538 		uint64_t reserved_18_19:2;
539 		uint64_t lmc0:1;
540 		uint64_t l2c:1;
541 		uint64_t reserved_15_15:1;
542 		uint64_t rad:1;
543 		uint64_t usb:1;
544 		uint64_t pow:1;
545 		uint64_t tim:1;
546 		uint64_t pko:1;
547 		uint64_t ipd:1;
548 		uint64_t reserved_8_8:1;
549 		uint64_t zip:1;
550 		uint64_t dfa:1;
551 		uint64_t fpa:1;
552 		uint64_t key:1;
553 		uint64_t sli:1;
554 		uint64_t gmx1:1;
555 		uint64_t gmx0:1;
556 		uint64_t mio:1;
557 #else
558 		uint64_t mio:1;
559 		uint64_t gmx0:1;
560 		uint64_t gmx1:1;
561 		uint64_t sli:1;
562 		uint64_t key:1;
563 		uint64_t fpa:1;
564 		uint64_t dfa:1;
565 		uint64_t zip:1;
566 		uint64_t reserved_8_8:1;
567 		uint64_t ipd:1;
568 		uint64_t pko:1;
569 		uint64_t tim:1;
570 		uint64_t pow:1;
571 		uint64_t usb:1;
572 		uint64_t rad:1;
573 		uint64_t reserved_15_15:1;
574 		uint64_t l2c:1;
575 		uint64_t lmc0:1;
576 		uint64_t reserved_18_19:2;
577 		uint64_t pip:1;
578 		uint64_t reserved_21_21:1;
579 		uint64_t asxpcs0:1;
580 		uint64_t asxpcs1:1;
581 		uint64_t reserved_24_24:1;
582 		uint64_t pem0:1;
583 		uint64_t pem1:1;
584 		uint64_t reserved_27_27:1;
585 		uint64_t agl:1;
586 		uint64_t reserved_29_29:1;
587 		uint64_t iob:1;
588 		uint64_t reserved_31_31:1;
589 		uint64_t srio0:1;
590 		uint64_t reserved_33_39:7;
591 		uint64_t dfm:1;
592 		uint64_t dpi:1;
593 		uint64_t ptp:1;
594 		uint64_t reserved_43_59:17;
595 		uint64_t srio2:1;
596 		uint64_t srio3:1;
597 		uint64_t reserved_62_63:2;
598 #endif
599 	} cn66xx;
600 	struct cvmx_ciu_block_int_cnf71xx {
601 #ifdef __BIG_ENDIAN_BITFIELD
602 		uint64_t reserved_43_63:21;
603 		uint64_t ptp:1;
604 		uint64_t dpi:1;
605 		uint64_t reserved_31_40:10;
606 		uint64_t iob:1;
607 		uint64_t reserved_27_29:3;
608 		uint64_t pem1:1;
609 		uint64_t pem0:1;
610 		uint64_t reserved_23_24:2;
611 		uint64_t asxpcs0:1;
612 		uint64_t reserved_21_21:1;
613 		uint64_t pip:1;
614 		uint64_t reserved_18_19:2;
615 		uint64_t lmc0:1;
616 		uint64_t l2c:1;
617 		uint64_t reserved_15_15:1;
618 		uint64_t rad:1;
619 		uint64_t usb:1;
620 		uint64_t pow:1;
621 		uint64_t tim:1;
622 		uint64_t pko:1;
623 		uint64_t ipd:1;
624 		uint64_t reserved_6_8:3;
625 		uint64_t fpa:1;
626 		uint64_t key:1;
627 		uint64_t sli:1;
628 		uint64_t reserved_2_2:1;
629 		uint64_t gmx0:1;
630 		uint64_t mio:1;
631 #else
632 		uint64_t mio:1;
633 		uint64_t gmx0:1;
634 		uint64_t reserved_2_2:1;
635 		uint64_t sli:1;
636 		uint64_t key:1;
637 		uint64_t fpa:1;
638 		uint64_t reserved_6_8:3;
639 		uint64_t ipd:1;
640 		uint64_t pko:1;
641 		uint64_t tim:1;
642 		uint64_t pow:1;
643 		uint64_t usb:1;
644 		uint64_t rad:1;
645 		uint64_t reserved_15_15:1;
646 		uint64_t l2c:1;
647 		uint64_t lmc0:1;
648 		uint64_t reserved_18_19:2;
649 		uint64_t pip:1;
650 		uint64_t reserved_21_21:1;
651 		uint64_t asxpcs0:1;
652 		uint64_t reserved_23_24:2;
653 		uint64_t pem0:1;
654 		uint64_t pem1:1;
655 		uint64_t reserved_27_29:3;
656 		uint64_t iob:1;
657 		uint64_t reserved_31_40:10;
658 		uint64_t dpi:1;
659 		uint64_t ptp:1;
660 		uint64_t reserved_43_63:21;
661 #endif
662 	} cnf71xx;
663 };
664 
665 union cvmx_ciu_dint {
666 	uint64_t u64;
667 	struct cvmx_ciu_dint_s {
668 #ifdef __BIG_ENDIAN_BITFIELD
669 		uint64_t reserved_32_63:32;
670 		uint64_t dint:32;
671 #else
672 		uint64_t dint:32;
673 		uint64_t reserved_32_63:32;
674 #endif
675 	} s;
676 	struct cvmx_ciu_dint_cn30xx {
677 #ifdef __BIG_ENDIAN_BITFIELD
678 		uint64_t reserved_1_63:63;
679 		uint64_t dint:1;
680 #else
681 		uint64_t dint:1;
682 		uint64_t reserved_1_63:63;
683 #endif
684 	} cn30xx;
685 	struct cvmx_ciu_dint_cn31xx {
686 #ifdef __BIG_ENDIAN_BITFIELD
687 		uint64_t reserved_2_63:62;
688 		uint64_t dint:2;
689 #else
690 		uint64_t dint:2;
691 		uint64_t reserved_2_63:62;
692 #endif
693 	} cn31xx;
694 	struct cvmx_ciu_dint_cn38xx {
695 #ifdef __BIG_ENDIAN_BITFIELD
696 		uint64_t reserved_16_63:48;
697 		uint64_t dint:16;
698 #else
699 		uint64_t dint:16;
700 		uint64_t reserved_16_63:48;
701 #endif
702 	} cn38xx;
703 	struct cvmx_ciu_dint_cn38xx cn38xxp2;
704 	struct cvmx_ciu_dint_cn31xx cn50xx;
705 	struct cvmx_ciu_dint_cn52xx {
706 #ifdef __BIG_ENDIAN_BITFIELD
707 		uint64_t reserved_4_63:60;
708 		uint64_t dint:4;
709 #else
710 		uint64_t dint:4;
711 		uint64_t reserved_4_63:60;
712 #endif
713 	} cn52xx;
714 	struct cvmx_ciu_dint_cn52xx cn52xxp1;
715 	struct cvmx_ciu_dint_cn56xx {
716 #ifdef __BIG_ENDIAN_BITFIELD
717 		uint64_t reserved_12_63:52;
718 		uint64_t dint:12;
719 #else
720 		uint64_t dint:12;
721 		uint64_t reserved_12_63:52;
722 #endif
723 	} cn56xx;
724 	struct cvmx_ciu_dint_cn56xx cn56xxp1;
725 	struct cvmx_ciu_dint_cn38xx cn58xx;
726 	struct cvmx_ciu_dint_cn38xx cn58xxp1;
727 	struct cvmx_ciu_dint_cn52xx cn61xx;
728 	struct cvmx_ciu_dint_cn63xx {
729 #ifdef __BIG_ENDIAN_BITFIELD
730 		uint64_t reserved_6_63:58;
731 		uint64_t dint:6;
732 #else
733 		uint64_t dint:6;
734 		uint64_t reserved_6_63:58;
735 #endif
736 	} cn63xx;
737 	struct cvmx_ciu_dint_cn63xx cn63xxp1;
738 	struct cvmx_ciu_dint_cn66xx {
739 #ifdef __BIG_ENDIAN_BITFIELD
740 		uint64_t reserved_10_63:54;
741 		uint64_t dint:10;
742 #else
743 		uint64_t dint:10;
744 		uint64_t reserved_10_63:54;
745 #endif
746 	} cn66xx;
747 	struct cvmx_ciu_dint_s cn68xx;
748 	struct cvmx_ciu_dint_s cn68xxp1;
749 	struct cvmx_ciu_dint_cn52xx cnf71xx;
750 };
751 
752 union cvmx_ciu_en2_iox_int {
753 	uint64_t u64;
754 	struct cvmx_ciu_en2_iox_int_s {
755 #ifdef __BIG_ENDIAN_BITFIELD
756 		uint64_t reserved_15_63:49;
757 		uint64_t endor:2;
758 		uint64_t eoi:1;
759 		uint64_t reserved_10_11:2;
760 		uint64_t timer:6;
761 		uint64_t reserved_0_3:4;
762 #else
763 		uint64_t reserved_0_3:4;
764 		uint64_t timer:6;
765 		uint64_t reserved_10_11:2;
766 		uint64_t eoi:1;
767 		uint64_t endor:2;
768 		uint64_t reserved_15_63:49;
769 #endif
770 	} s;
771 	struct cvmx_ciu_en2_iox_int_cn61xx {
772 #ifdef __BIG_ENDIAN_BITFIELD
773 		uint64_t reserved_10_63:54;
774 		uint64_t timer:6;
775 		uint64_t reserved_0_3:4;
776 #else
777 		uint64_t reserved_0_3:4;
778 		uint64_t timer:6;
779 		uint64_t reserved_10_63:54;
780 #endif
781 	} cn61xx;
782 	struct cvmx_ciu_en2_iox_int_cn61xx cn66xx;
783 	struct cvmx_ciu_en2_iox_int_s cnf71xx;
784 };
785 
786 union cvmx_ciu_en2_iox_int_w1c {
787 	uint64_t u64;
788 	struct cvmx_ciu_en2_iox_int_w1c_s {
789 #ifdef __BIG_ENDIAN_BITFIELD
790 		uint64_t reserved_15_63:49;
791 		uint64_t endor:2;
792 		uint64_t eoi:1;
793 		uint64_t reserved_10_11:2;
794 		uint64_t timer:6;
795 		uint64_t reserved_0_3:4;
796 #else
797 		uint64_t reserved_0_3:4;
798 		uint64_t timer:6;
799 		uint64_t reserved_10_11:2;
800 		uint64_t eoi:1;
801 		uint64_t endor:2;
802 		uint64_t reserved_15_63:49;
803 #endif
804 	} s;
805 	struct cvmx_ciu_en2_iox_int_w1c_cn61xx {
806 #ifdef __BIG_ENDIAN_BITFIELD
807 		uint64_t reserved_10_63:54;
808 		uint64_t timer:6;
809 		uint64_t reserved_0_3:4;
810 #else
811 		uint64_t reserved_0_3:4;
812 		uint64_t timer:6;
813 		uint64_t reserved_10_63:54;
814 #endif
815 	} cn61xx;
816 	struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx;
817 	struct cvmx_ciu_en2_iox_int_w1c_s cnf71xx;
818 };
819 
820 union cvmx_ciu_en2_iox_int_w1s {
821 	uint64_t u64;
822 	struct cvmx_ciu_en2_iox_int_w1s_s {
823 #ifdef __BIG_ENDIAN_BITFIELD
824 		uint64_t reserved_15_63:49;
825 		uint64_t endor:2;
826 		uint64_t eoi:1;
827 		uint64_t reserved_10_11:2;
828 		uint64_t timer:6;
829 		uint64_t reserved_0_3:4;
830 #else
831 		uint64_t reserved_0_3:4;
832 		uint64_t timer:6;
833 		uint64_t reserved_10_11:2;
834 		uint64_t eoi:1;
835 		uint64_t endor:2;
836 		uint64_t reserved_15_63:49;
837 #endif
838 	} s;
839 	struct cvmx_ciu_en2_iox_int_w1s_cn61xx {
840 #ifdef __BIG_ENDIAN_BITFIELD
841 		uint64_t reserved_10_63:54;
842 		uint64_t timer:6;
843 		uint64_t reserved_0_3:4;
844 #else
845 		uint64_t reserved_0_3:4;
846 		uint64_t timer:6;
847 		uint64_t reserved_10_63:54;
848 #endif
849 	} cn61xx;
850 	struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx;
851 	struct cvmx_ciu_en2_iox_int_w1s_s cnf71xx;
852 };
853 
854 union cvmx_ciu_en2_ppx_ip2 {
855 	uint64_t u64;
856 	struct cvmx_ciu_en2_ppx_ip2_s {
857 #ifdef __BIG_ENDIAN_BITFIELD
858 		uint64_t reserved_15_63:49;
859 		uint64_t endor:2;
860 		uint64_t eoi:1;
861 		uint64_t reserved_10_11:2;
862 		uint64_t timer:6;
863 		uint64_t reserved_0_3:4;
864 #else
865 		uint64_t reserved_0_3:4;
866 		uint64_t timer:6;
867 		uint64_t reserved_10_11:2;
868 		uint64_t eoi:1;
869 		uint64_t endor:2;
870 		uint64_t reserved_15_63:49;
871 #endif
872 	} s;
873 	struct cvmx_ciu_en2_ppx_ip2_cn61xx {
874 #ifdef __BIG_ENDIAN_BITFIELD
875 		uint64_t reserved_10_63:54;
876 		uint64_t timer:6;
877 		uint64_t reserved_0_3:4;
878 #else
879 		uint64_t reserved_0_3:4;
880 		uint64_t timer:6;
881 		uint64_t reserved_10_63:54;
882 #endif
883 	} cn61xx;
884 	struct cvmx_ciu_en2_ppx_ip2_cn61xx cn66xx;
885 	struct cvmx_ciu_en2_ppx_ip2_s cnf71xx;
886 };
887 
888 union cvmx_ciu_en2_ppx_ip2_w1c {
889 	uint64_t u64;
890 	struct cvmx_ciu_en2_ppx_ip2_w1c_s {
891 #ifdef __BIG_ENDIAN_BITFIELD
892 		uint64_t reserved_15_63:49;
893 		uint64_t endor:2;
894 		uint64_t eoi:1;
895 		uint64_t reserved_10_11:2;
896 		uint64_t timer:6;
897 		uint64_t reserved_0_3:4;
898 #else
899 		uint64_t reserved_0_3:4;
900 		uint64_t timer:6;
901 		uint64_t reserved_10_11:2;
902 		uint64_t eoi:1;
903 		uint64_t endor:2;
904 		uint64_t reserved_15_63:49;
905 #endif
906 	} s;
907 	struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx {
908 #ifdef __BIG_ENDIAN_BITFIELD
909 		uint64_t reserved_10_63:54;
910 		uint64_t timer:6;
911 		uint64_t reserved_0_3:4;
912 #else
913 		uint64_t reserved_0_3:4;
914 		uint64_t timer:6;
915 		uint64_t reserved_10_63:54;
916 #endif
917 	} cn61xx;
918 	struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx;
919 	struct cvmx_ciu_en2_ppx_ip2_w1c_s cnf71xx;
920 };
921 
922 union cvmx_ciu_en2_ppx_ip2_w1s {
923 	uint64_t u64;
924 	struct cvmx_ciu_en2_ppx_ip2_w1s_s {
925 #ifdef __BIG_ENDIAN_BITFIELD
926 		uint64_t reserved_15_63:49;
927 		uint64_t endor:2;
928 		uint64_t eoi:1;
929 		uint64_t reserved_10_11:2;
930 		uint64_t timer:6;
931 		uint64_t reserved_0_3:4;
932 #else
933 		uint64_t reserved_0_3:4;
934 		uint64_t timer:6;
935 		uint64_t reserved_10_11:2;
936 		uint64_t eoi:1;
937 		uint64_t endor:2;
938 		uint64_t reserved_15_63:49;
939 #endif
940 	} s;
941 	struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx {
942 #ifdef __BIG_ENDIAN_BITFIELD
943 		uint64_t reserved_10_63:54;
944 		uint64_t timer:6;
945 		uint64_t reserved_0_3:4;
946 #else
947 		uint64_t reserved_0_3:4;
948 		uint64_t timer:6;
949 		uint64_t reserved_10_63:54;
950 #endif
951 	} cn61xx;
952 	struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx;
953 	struct cvmx_ciu_en2_ppx_ip2_w1s_s cnf71xx;
954 };
955 
956 union cvmx_ciu_en2_ppx_ip3 {
957 	uint64_t u64;
958 	struct cvmx_ciu_en2_ppx_ip3_s {
959 #ifdef __BIG_ENDIAN_BITFIELD
960 		uint64_t reserved_15_63:49;
961 		uint64_t endor:2;
962 		uint64_t eoi:1;
963 		uint64_t reserved_10_11:2;
964 		uint64_t timer:6;
965 		uint64_t reserved_0_3:4;
966 #else
967 		uint64_t reserved_0_3:4;
968 		uint64_t timer:6;
969 		uint64_t reserved_10_11:2;
970 		uint64_t eoi:1;
971 		uint64_t endor:2;
972 		uint64_t reserved_15_63:49;
973 #endif
974 	} s;
975 	struct cvmx_ciu_en2_ppx_ip3_cn61xx {
976 #ifdef __BIG_ENDIAN_BITFIELD
977 		uint64_t reserved_10_63:54;
978 		uint64_t timer:6;
979 		uint64_t reserved_0_3:4;
980 #else
981 		uint64_t reserved_0_3:4;
982 		uint64_t timer:6;
983 		uint64_t reserved_10_63:54;
984 #endif
985 	} cn61xx;
986 	struct cvmx_ciu_en2_ppx_ip3_cn61xx cn66xx;
987 	struct cvmx_ciu_en2_ppx_ip3_s cnf71xx;
988 };
989 
990 union cvmx_ciu_en2_ppx_ip3_w1c {
991 	uint64_t u64;
992 	struct cvmx_ciu_en2_ppx_ip3_w1c_s {
993 #ifdef __BIG_ENDIAN_BITFIELD
994 		uint64_t reserved_15_63:49;
995 		uint64_t endor:2;
996 		uint64_t eoi:1;
997 		uint64_t reserved_10_11:2;
998 		uint64_t timer:6;
999 		uint64_t reserved_0_3:4;
1000 #else
1001 		uint64_t reserved_0_3:4;
1002 		uint64_t timer:6;
1003 		uint64_t reserved_10_11:2;
1004 		uint64_t eoi:1;
1005 		uint64_t endor:2;
1006 		uint64_t reserved_15_63:49;
1007 #endif
1008 	} s;
1009 	struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx {
1010 #ifdef __BIG_ENDIAN_BITFIELD
1011 		uint64_t reserved_10_63:54;
1012 		uint64_t timer:6;
1013 		uint64_t reserved_0_3:4;
1014 #else
1015 		uint64_t reserved_0_3:4;
1016 		uint64_t timer:6;
1017 		uint64_t reserved_10_63:54;
1018 #endif
1019 	} cn61xx;
1020 	struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx;
1021 	struct cvmx_ciu_en2_ppx_ip3_w1c_s cnf71xx;
1022 };
1023 
1024 union cvmx_ciu_en2_ppx_ip3_w1s {
1025 	uint64_t u64;
1026 	struct cvmx_ciu_en2_ppx_ip3_w1s_s {
1027 #ifdef __BIG_ENDIAN_BITFIELD
1028 		uint64_t reserved_15_63:49;
1029 		uint64_t endor:2;
1030 		uint64_t eoi:1;
1031 		uint64_t reserved_10_11:2;
1032 		uint64_t timer:6;
1033 		uint64_t reserved_0_3:4;
1034 #else
1035 		uint64_t reserved_0_3:4;
1036 		uint64_t timer:6;
1037 		uint64_t reserved_10_11:2;
1038 		uint64_t eoi:1;
1039 		uint64_t endor:2;
1040 		uint64_t reserved_15_63:49;
1041 #endif
1042 	} s;
1043 	struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx {
1044 #ifdef __BIG_ENDIAN_BITFIELD
1045 		uint64_t reserved_10_63:54;
1046 		uint64_t timer:6;
1047 		uint64_t reserved_0_3:4;
1048 #else
1049 		uint64_t reserved_0_3:4;
1050 		uint64_t timer:6;
1051 		uint64_t reserved_10_63:54;
1052 #endif
1053 	} cn61xx;
1054 	struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx;
1055 	struct cvmx_ciu_en2_ppx_ip3_w1s_s cnf71xx;
1056 };
1057 
1058 union cvmx_ciu_en2_ppx_ip4 {
1059 	uint64_t u64;
1060 	struct cvmx_ciu_en2_ppx_ip4_s {
1061 #ifdef __BIG_ENDIAN_BITFIELD
1062 		uint64_t reserved_15_63:49;
1063 		uint64_t endor:2;
1064 		uint64_t eoi:1;
1065 		uint64_t reserved_10_11:2;
1066 		uint64_t timer:6;
1067 		uint64_t reserved_0_3:4;
1068 #else
1069 		uint64_t reserved_0_3:4;
1070 		uint64_t timer:6;
1071 		uint64_t reserved_10_11:2;
1072 		uint64_t eoi:1;
1073 		uint64_t endor:2;
1074 		uint64_t reserved_15_63:49;
1075 #endif
1076 	} s;
1077 	struct cvmx_ciu_en2_ppx_ip4_cn61xx {
1078 #ifdef __BIG_ENDIAN_BITFIELD
1079 		uint64_t reserved_10_63:54;
1080 		uint64_t timer:6;
1081 		uint64_t reserved_0_3:4;
1082 #else
1083 		uint64_t reserved_0_3:4;
1084 		uint64_t timer:6;
1085 		uint64_t reserved_10_63:54;
1086 #endif
1087 	} cn61xx;
1088 	struct cvmx_ciu_en2_ppx_ip4_cn61xx cn66xx;
1089 	struct cvmx_ciu_en2_ppx_ip4_s cnf71xx;
1090 };
1091 
1092 union cvmx_ciu_en2_ppx_ip4_w1c {
1093 	uint64_t u64;
1094 	struct cvmx_ciu_en2_ppx_ip4_w1c_s {
1095 #ifdef __BIG_ENDIAN_BITFIELD
1096 		uint64_t reserved_15_63:49;
1097 		uint64_t endor:2;
1098 		uint64_t eoi:1;
1099 		uint64_t reserved_10_11:2;
1100 		uint64_t timer:6;
1101 		uint64_t reserved_0_3:4;
1102 #else
1103 		uint64_t reserved_0_3:4;
1104 		uint64_t timer:6;
1105 		uint64_t reserved_10_11:2;
1106 		uint64_t eoi:1;
1107 		uint64_t endor:2;
1108 		uint64_t reserved_15_63:49;
1109 #endif
1110 	} s;
1111 	struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx {
1112 #ifdef __BIG_ENDIAN_BITFIELD
1113 		uint64_t reserved_10_63:54;
1114 		uint64_t timer:6;
1115 		uint64_t reserved_0_3:4;
1116 #else
1117 		uint64_t reserved_0_3:4;
1118 		uint64_t timer:6;
1119 		uint64_t reserved_10_63:54;
1120 #endif
1121 	} cn61xx;
1122 	struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx;
1123 	struct cvmx_ciu_en2_ppx_ip4_w1c_s cnf71xx;
1124 };
1125 
1126 union cvmx_ciu_en2_ppx_ip4_w1s {
1127 	uint64_t u64;
1128 	struct cvmx_ciu_en2_ppx_ip4_w1s_s {
1129 #ifdef __BIG_ENDIAN_BITFIELD
1130 		uint64_t reserved_15_63:49;
1131 		uint64_t endor:2;
1132 		uint64_t eoi:1;
1133 		uint64_t reserved_10_11:2;
1134 		uint64_t timer:6;
1135 		uint64_t reserved_0_3:4;
1136 #else
1137 		uint64_t reserved_0_3:4;
1138 		uint64_t timer:6;
1139 		uint64_t reserved_10_11:2;
1140 		uint64_t eoi:1;
1141 		uint64_t endor:2;
1142 		uint64_t reserved_15_63:49;
1143 #endif
1144 	} s;
1145 	struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx {
1146 #ifdef __BIG_ENDIAN_BITFIELD
1147 		uint64_t reserved_10_63:54;
1148 		uint64_t timer:6;
1149 		uint64_t reserved_0_3:4;
1150 #else
1151 		uint64_t reserved_0_3:4;
1152 		uint64_t timer:6;
1153 		uint64_t reserved_10_63:54;
1154 #endif
1155 	} cn61xx;
1156 	struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx;
1157 	struct cvmx_ciu_en2_ppx_ip4_w1s_s cnf71xx;
1158 };
1159 
1160 union cvmx_ciu_fuse {
1161 	uint64_t u64;
1162 	struct cvmx_ciu_fuse_s {
1163 #ifdef __BIG_ENDIAN_BITFIELD
1164 		uint64_t reserved_32_63:32;
1165 		uint64_t fuse:32;
1166 #else
1167 		uint64_t fuse:32;
1168 		uint64_t reserved_32_63:32;
1169 #endif
1170 	} s;
1171 	struct cvmx_ciu_fuse_cn30xx {
1172 #ifdef __BIG_ENDIAN_BITFIELD
1173 		uint64_t reserved_1_63:63;
1174 		uint64_t fuse:1;
1175 #else
1176 		uint64_t fuse:1;
1177 		uint64_t reserved_1_63:63;
1178 #endif
1179 	} cn30xx;
1180 	struct cvmx_ciu_fuse_cn31xx {
1181 #ifdef __BIG_ENDIAN_BITFIELD
1182 		uint64_t reserved_2_63:62;
1183 		uint64_t fuse:2;
1184 #else
1185 		uint64_t fuse:2;
1186 		uint64_t reserved_2_63:62;
1187 #endif
1188 	} cn31xx;
1189 	struct cvmx_ciu_fuse_cn38xx {
1190 #ifdef __BIG_ENDIAN_BITFIELD
1191 		uint64_t reserved_16_63:48;
1192 		uint64_t fuse:16;
1193 #else
1194 		uint64_t fuse:16;
1195 		uint64_t reserved_16_63:48;
1196 #endif
1197 	} cn38xx;
1198 	struct cvmx_ciu_fuse_cn38xx cn38xxp2;
1199 	struct cvmx_ciu_fuse_cn31xx cn50xx;
1200 	struct cvmx_ciu_fuse_cn52xx {
1201 #ifdef __BIG_ENDIAN_BITFIELD
1202 		uint64_t reserved_4_63:60;
1203 		uint64_t fuse:4;
1204 #else
1205 		uint64_t fuse:4;
1206 		uint64_t reserved_4_63:60;
1207 #endif
1208 	} cn52xx;
1209 	struct cvmx_ciu_fuse_cn52xx cn52xxp1;
1210 	struct cvmx_ciu_fuse_cn56xx {
1211 #ifdef __BIG_ENDIAN_BITFIELD
1212 		uint64_t reserved_12_63:52;
1213 		uint64_t fuse:12;
1214 #else
1215 		uint64_t fuse:12;
1216 		uint64_t reserved_12_63:52;
1217 #endif
1218 	} cn56xx;
1219 	struct cvmx_ciu_fuse_cn56xx cn56xxp1;
1220 	struct cvmx_ciu_fuse_cn38xx cn58xx;
1221 	struct cvmx_ciu_fuse_cn38xx cn58xxp1;
1222 	struct cvmx_ciu_fuse_cn52xx cn61xx;
1223 	struct cvmx_ciu_fuse_cn63xx {
1224 #ifdef __BIG_ENDIAN_BITFIELD
1225 		uint64_t reserved_6_63:58;
1226 		uint64_t fuse:6;
1227 #else
1228 		uint64_t fuse:6;
1229 		uint64_t reserved_6_63:58;
1230 #endif
1231 	} cn63xx;
1232 	struct cvmx_ciu_fuse_cn63xx cn63xxp1;
1233 	struct cvmx_ciu_fuse_cn66xx {
1234 #ifdef __BIG_ENDIAN_BITFIELD
1235 		uint64_t reserved_10_63:54;
1236 		uint64_t fuse:10;
1237 #else
1238 		uint64_t fuse:10;
1239 		uint64_t reserved_10_63:54;
1240 #endif
1241 	} cn66xx;
1242 	struct cvmx_ciu_fuse_s cn68xx;
1243 	struct cvmx_ciu_fuse_s cn68xxp1;
1244 	struct cvmx_ciu_fuse_cn52xx cnf71xx;
1245 };
1246 
1247 union cvmx_ciu_gstop {
1248 	uint64_t u64;
1249 	struct cvmx_ciu_gstop_s {
1250 #ifdef __BIG_ENDIAN_BITFIELD
1251 		uint64_t reserved_1_63:63;
1252 		uint64_t gstop:1;
1253 #else
1254 		uint64_t gstop:1;
1255 		uint64_t reserved_1_63:63;
1256 #endif
1257 	} s;
1258 	struct cvmx_ciu_gstop_s cn30xx;
1259 	struct cvmx_ciu_gstop_s cn31xx;
1260 	struct cvmx_ciu_gstop_s cn38xx;
1261 	struct cvmx_ciu_gstop_s cn38xxp2;
1262 	struct cvmx_ciu_gstop_s cn50xx;
1263 	struct cvmx_ciu_gstop_s cn52xx;
1264 	struct cvmx_ciu_gstop_s cn52xxp1;
1265 	struct cvmx_ciu_gstop_s cn56xx;
1266 	struct cvmx_ciu_gstop_s cn56xxp1;
1267 	struct cvmx_ciu_gstop_s cn58xx;
1268 	struct cvmx_ciu_gstop_s cn58xxp1;
1269 	struct cvmx_ciu_gstop_s cn61xx;
1270 	struct cvmx_ciu_gstop_s cn63xx;
1271 	struct cvmx_ciu_gstop_s cn63xxp1;
1272 	struct cvmx_ciu_gstop_s cn66xx;
1273 	struct cvmx_ciu_gstop_s cn68xx;
1274 	struct cvmx_ciu_gstop_s cn68xxp1;
1275 	struct cvmx_ciu_gstop_s cnf71xx;
1276 };
1277 
1278 union cvmx_ciu_intx_en0 {
1279 	uint64_t u64;
1280 	struct cvmx_ciu_intx_en0_s {
1281 #ifdef __BIG_ENDIAN_BITFIELD
1282 		uint64_t bootdma:1;
1283 		uint64_t mii:1;
1284 		uint64_t ipdppthr:1;
1285 		uint64_t powiq:1;
1286 		uint64_t twsi2:1;
1287 		uint64_t mpi:1;
1288 		uint64_t pcm:1;
1289 		uint64_t usb:1;
1290 		uint64_t timer:4;
1291 		uint64_t key_zero:1;
1292 		uint64_t ipd_drp:1;
1293 		uint64_t gmx_drp:2;
1294 		uint64_t trace:1;
1295 		uint64_t rml:1;
1296 		uint64_t twsi:1;
1297 		uint64_t reserved_44_44:1;
1298 		uint64_t pci_msi:4;
1299 		uint64_t pci_int:4;
1300 		uint64_t uart:2;
1301 		uint64_t mbox:2;
1302 		uint64_t gpio:16;
1303 		uint64_t workq:16;
1304 #else
1305 		uint64_t workq:16;
1306 		uint64_t gpio:16;
1307 		uint64_t mbox:2;
1308 		uint64_t uart:2;
1309 		uint64_t pci_int:4;
1310 		uint64_t pci_msi:4;
1311 		uint64_t reserved_44_44:1;
1312 		uint64_t twsi:1;
1313 		uint64_t rml:1;
1314 		uint64_t trace:1;
1315 		uint64_t gmx_drp:2;
1316 		uint64_t ipd_drp:1;
1317 		uint64_t key_zero:1;
1318 		uint64_t timer:4;
1319 		uint64_t usb:1;
1320 		uint64_t pcm:1;
1321 		uint64_t mpi:1;
1322 		uint64_t twsi2:1;
1323 		uint64_t powiq:1;
1324 		uint64_t ipdppthr:1;
1325 		uint64_t mii:1;
1326 		uint64_t bootdma:1;
1327 #endif
1328 	} s;
1329 	struct cvmx_ciu_intx_en0_cn30xx {
1330 #ifdef __BIG_ENDIAN_BITFIELD
1331 		uint64_t reserved_59_63:5;
1332 		uint64_t mpi:1;
1333 		uint64_t pcm:1;
1334 		uint64_t usb:1;
1335 		uint64_t timer:4;
1336 		uint64_t reserved_51_51:1;
1337 		uint64_t ipd_drp:1;
1338 		uint64_t reserved_49_49:1;
1339 		uint64_t gmx_drp:1;
1340 		uint64_t reserved_47_47:1;
1341 		uint64_t rml:1;
1342 		uint64_t twsi:1;
1343 		uint64_t reserved_44_44:1;
1344 		uint64_t pci_msi:4;
1345 		uint64_t pci_int:4;
1346 		uint64_t uart:2;
1347 		uint64_t mbox:2;
1348 		uint64_t gpio:16;
1349 		uint64_t workq:16;
1350 #else
1351 		uint64_t workq:16;
1352 		uint64_t gpio:16;
1353 		uint64_t mbox:2;
1354 		uint64_t uart:2;
1355 		uint64_t pci_int:4;
1356 		uint64_t pci_msi:4;
1357 		uint64_t reserved_44_44:1;
1358 		uint64_t twsi:1;
1359 		uint64_t rml:1;
1360 		uint64_t reserved_47_47:1;
1361 		uint64_t gmx_drp:1;
1362 		uint64_t reserved_49_49:1;
1363 		uint64_t ipd_drp:1;
1364 		uint64_t reserved_51_51:1;
1365 		uint64_t timer:4;
1366 		uint64_t usb:1;
1367 		uint64_t pcm:1;
1368 		uint64_t mpi:1;
1369 		uint64_t reserved_59_63:5;
1370 #endif
1371 	} cn30xx;
1372 	struct cvmx_ciu_intx_en0_cn31xx {
1373 #ifdef __BIG_ENDIAN_BITFIELD
1374 		uint64_t reserved_59_63:5;
1375 		uint64_t mpi:1;
1376 		uint64_t pcm:1;
1377 		uint64_t usb:1;
1378 		uint64_t timer:4;
1379 		uint64_t reserved_51_51:1;
1380 		uint64_t ipd_drp:1;
1381 		uint64_t reserved_49_49:1;
1382 		uint64_t gmx_drp:1;
1383 		uint64_t trace:1;
1384 		uint64_t rml:1;
1385 		uint64_t twsi:1;
1386 		uint64_t reserved_44_44:1;
1387 		uint64_t pci_msi:4;
1388 		uint64_t pci_int:4;
1389 		uint64_t uart:2;
1390 		uint64_t mbox:2;
1391 		uint64_t gpio:16;
1392 		uint64_t workq:16;
1393 #else
1394 		uint64_t workq:16;
1395 		uint64_t gpio:16;
1396 		uint64_t mbox:2;
1397 		uint64_t uart:2;
1398 		uint64_t pci_int:4;
1399 		uint64_t pci_msi:4;
1400 		uint64_t reserved_44_44:1;
1401 		uint64_t twsi:1;
1402 		uint64_t rml:1;
1403 		uint64_t trace:1;
1404 		uint64_t gmx_drp:1;
1405 		uint64_t reserved_49_49:1;
1406 		uint64_t ipd_drp:1;
1407 		uint64_t reserved_51_51:1;
1408 		uint64_t timer:4;
1409 		uint64_t usb:1;
1410 		uint64_t pcm:1;
1411 		uint64_t mpi:1;
1412 		uint64_t reserved_59_63:5;
1413 #endif
1414 	} cn31xx;
1415 	struct cvmx_ciu_intx_en0_cn38xx {
1416 #ifdef __BIG_ENDIAN_BITFIELD
1417 		uint64_t reserved_56_63:8;
1418 		uint64_t timer:4;
1419 		uint64_t key_zero:1;
1420 		uint64_t ipd_drp:1;
1421 		uint64_t gmx_drp:2;
1422 		uint64_t trace:1;
1423 		uint64_t rml:1;
1424 		uint64_t twsi:1;
1425 		uint64_t reserved_44_44:1;
1426 		uint64_t pci_msi:4;
1427 		uint64_t pci_int:4;
1428 		uint64_t uart:2;
1429 		uint64_t mbox:2;
1430 		uint64_t gpio:16;
1431 		uint64_t workq:16;
1432 #else
1433 		uint64_t workq:16;
1434 		uint64_t gpio:16;
1435 		uint64_t mbox:2;
1436 		uint64_t uart:2;
1437 		uint64_t pci_int:4;
1438 		uint64_t pci_msi:4;
1439 		uint64_t reserved_44_44:1;
1440 		uint64_t twsi:1;
1441 		uint64_t rml:1;
1442 		uint64_t trace:1;
1443 		uint64_t gmx_drp:2;
1444 		uint64_t ipd_drp:1;
1445 		uint64_t key_zero:1;
1446 		uint64_t timer:4;
1447 		uint64_t reserved_56_63:8;
1448 #endif
1449 	} cn38xx;
1450 	struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
1451 	struct cvmx_ciu_intx_en0_cn30xx cn50xx;
1452 	struct cvmx_ciu_intx_en0_cn52xx {
1453 #ifdef __BIG_ENDIAN_BITFIELD
1454 		uint64_t bootdma:1;
1455 		uint64_t mii:1;
1456 		uint64_t ipdppthr:1;
1457 		uint64_t powiq:1;
1458 		uint64_t twsi2:1;
1459 		uint64_t reserved_57_58:2;
1460 		uint64_t usb:1;
1461 		uint64_t timer:4;
1462 		uint64_t reserved_51_51:1;
1463 		uint64_t ipd_drp:1;
1464 		uint64_t reserved_49_49:1;
1465 		uint64_t gmx_drp:1;
1466 		uint64_t trace:1;
1467 		uint64_t rml:1;
1468 		uint64_t twsi:1;
1469 		uint64_t reserved_44_44:1;
1470 		uint64_t pci_msi:4;
1471 		uint64_t pci_int:4;
1472 		uint64_t uart:2;
1473 		uint64_t mbox:2;
1474 		uint64_t gpio:16;
1475 		uint64_t workq:16;
1476 #else
1477 		uint64_t workq:16;
1478 		uint64_t gpio:16;
1479 		uint64_t mbox:2;
1480 		uint64_t uart:2;
1481 		uint64_t pci_int:4;
1482 		uint64_t pci_msi:4;
1483 		uint64_t reserved_44_44:1;
1484 		uint64_t twsi:1;
1485 		uint64_t rml:1;
1486 		uint64_t trace:1;
1487 		uint64_t gmx_drp:1;
1488 		uint64_t reserved_49_49:1;
1489 		uint64_t ipd_drp:1;
1490 		uint64_t reserved_51_51:1;
1491 		uint64_t timer:4;
1492 		uint64_t usb:1;
1493 		uint64_t reserved_57_58:2;
1494 		uint64_t twsi2:1;
1495 		uint64_t powiq:1;
1496 		uint64_t ipdppthr:1;
1497 		uint64_t mii:1;
1498 		uint64_t bootdma:1;
1499 #endif
1500 	} cn52xx;
1501 	struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
1502 	struct cvmx_ciu_intx_en0_cn56xx {
1503 #ifdef __BIG_ENDIAN_BITFIELD
1504 		uint64_t bootdma:1;
1505 		uint64_t mii:1;
1506 		uint64_t ipdppthr:1;
1507 		uint64_t powiq:1;
1508 		uint64_t twsi2:1;
1509 		uint64_t reserved_57_58:2;
1510 		uint64_t usb:1;
1511 		uint64_t timer:4;
1512 		uint64_t key_zero:1;
1513 		uint64_t ipd_drp:1;
1514 		uint64_t gmx_drp:2;
1515 		uint64_t trace:1;
1516 		uint64_t rml:1;
1517 		uint64_t twsi:1;
1518 		uint64_t reserved_44_44:1;
1519 		uint64_t pci_msi:4;
1520 		uint64_t pci_int:4;
1521 		uint64_t uart:2;
1522 		uint64_t mbox:2;
1523 		uint64_t gpio:16;
1524 		uint64_t workq:16;
1525 #else
1526 		uint64_t workq:16;
1527 		uint64_t gpio:16;
1528 		uint64_t mbox:2;
1529 		uint64_t uart:2;
1530 		uint64_t pci_int:4;
1531 		uint64_t pci_msi:4;
1532 		uint64_t reserved_44_44:1;
1533 		uint64_t twsi:1;
1534 		uint64_t rml:1;
1535 		uint64_t trace:1;
1536 		uint64_t gmx_drp:2;
1537 		uint64_t ipd_drp:1;
1538 		uint64_t key_zero:1;
1539 		uint64_t timer:4;
1540 		uint64_t usb:1;
1541 		uint64_t reserved_57_58:2;
1542 		uint64_t twsi2:1;
1543 		uint64_t powiq:1;
1544 		uint64_t ipdppthr:1;
1545 		uint64_t mii:1;
1546 		uint64_t bootdma:1;
1547 #endif
1548 	} cn56xx;
1549 	struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
1550 	struct cvmx_ciu_intx_en0_cn38xx cn58xx;
1551 	struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
1552 	struct cvmx_ciu_intx_en0_cn61xx {
1553 #ifdef __BIG_ENDIAN_BITFIELD
1554 		uint64_t bootdma:1;
1555 		uint64_t mii:1;
1556 		uint64_t ipdppthr:1;
1557 		uint64_t powiq:1;
1558 		uint64_t twsi2:1;
1559 		uint64_t mpi:1;
1560 		uint64_t pcm:1;
1561 		uint64_t usb:1;
1562 		uint64_t timer:4;
1563 		uint64_t reserved_51_51:1;
1564 		uint64_t ipd_drp:1;
1565 		uint64_t gmx_drp:2;
1566 		uint64_t trace:1;
1567 		uint64_t rml:1;
1568 		uint64_t twsi:1;
1569 		uint64_t reserved_44_44:1;
1570 		uint64_t pci_msi:4;
1571 		uint64_t pci_int:4;
1572 		uint64_t uart:2;
1573 		uint64_t mbox:2;
1574 		uint64_t gpio:16;
1575 		uint64_t workq:16;
1576 #else
1577 		uint64_t workq:16;
1578 		uint64_t gpio:16;
1579 		uint64_t mbox:2;
1580 		uint64_t uart:2;
1581 		uint64_t pci_int:4;
1582 		uint64_t pci_msi:4;
1583 		uint64_t reserved_44_44:1;
1584 		uint64_t twsi:1;
1585 		uint64_t rml:1;
1586 		uint64_t trace:1;
1587 		uint64_t gmx_drp:2;
1588 		uint64_t ipd_drp:1;
1589 		uint64_t reserved_51_51:1;
1590 		uint64_t timer:4;
1591 		uint64_t usb:1;
1592 		uint64_t pcm:1;
1593 		uint64_t mpi:1;
1594 		uint64_t twsi2:1;
1595 		uint64_t powiq:1;
1596 		uint64_t ipdppthr:1;
1597 		uint64_t mii:1;
1598 		uint64_t bootdma:1;
1599 #endif
1600 	} cn61xx;
1601 	struct cvmx_ciu_intx_en0_cn52xx cn63xx;
1602 	struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
1603 	struct cvmx_ciu_intx_en0_cn66xx {
1604 #ifdef __BIG_ENDIAN_BITFIELD
1605 		uint64_t bootdma:1;
1606 		uint64_t mii:1;
1607 		uint64_t ipdppthr:1;
1608 		uint64_t powiq:1;
1609 		uint64_t twsi2:1;
1610 		uint64_t mpi:1;
1611 		uint64_t reserved_57_57:1;
1612 		uint64_t usb:1;
1613 		uint64_t timer:4;
1614 		uint64_t reserved_51_51:1;
1615 		uint64_t ipd_drp:1;
1616 		uint64_t gmx_drp:2;
1617 		uint64_t trace:1;
1618 		uint64_t rml:1;
1619 		uint64_t twsi:1;
1620 		uint64_t reserved_44_44:1;
1621 		uint64_t pci_msi:4;
1622 		uint64_t pci_int:4;
1623 		uint64_t uart:2;
1624 		uint64_t mbox:2;
1625 		uint64_t gpio:16;
1626 		uint64_t workq:16;
1627 #else
1628 		uint64_t workq:16;
1629 		uint64_t gpio:16;
1630 		uint64_t mbox:2;
1631 		uint64_t uart:2;
1632 		uint64_t pci_int:4;
1633 		uint64_t pci_msi:4;
1634 		uint64_t reserved_44_44:1;
1635 		uint64_t twsi:1;
1636 		uint64_t rml:1;
1637 		uint64_t trace:1;
1638 		uint64_t gmx_drp:2;
1639 		uint64_t ipd_drp:1;
1640 		uint64_t reserved_51_51:1;
1641 		uint64_t timer:4;
1642 		uint64_t usb:1;
1643 		uint64_t reserved_57_57:1;
1644 		uint64_t mpi:1;
1645 		uint64_t twsi2:1;
1646 		uint64_t powiq:1;
1647 		uint64_t ipdppthr:1;
1648 		uint64_t mii:1;
1649 		uint64_t bootdma:1;
1650 #endif
1651 	} cn66xx;
1652 	struct cvmx_ciu_intx_en0_cnf71xx {
1653 #ifdef __BIG_ENDIAN_BITFIELD
1654 		uint64_t bootdma:1;
1655 		uint64_t reserved_62_62:1;
1656 		uint64_t ipdppthr:1;
1657 		uint64_t powiq:1;
1658 		uint64_t twsi2:1;
1659 		uint64_t mpi:1;
1660 		uint64_t pcm:1;
1661 		uint64_t usb:1;
1662 		uint64_t timer:4;
1663 		uint64_t reserved_51_51:1;
1664 		uint64_t ipd_drp:1;
1665 		uint64_t reserved_49_49:1;
1666 		uint64_t gmx_drp:1;
1667 		uint64_t trace:1;
1668 		uint64_t rml:1;
1669 		uint64_t twsi:1;
1670 		uint64_t reserved_44_44:1;
1671 		uint64_t pci_msi:4;
1672 		uint64_t pci_int:4;
1673 		uint64_t uart:2;
1674 		uint64_t mbox:2;
1675 		uint64_t gpio:16;
1676 		uint64_t workq:16;
1677 #else
1678 		uint64_t workq:16;
1679 		uint64_t gpio:16;
1680 		uint64_t mbox:2;
1681 		uint64_t uart:2;
1682 		uint64_t pci_int:4;
1683 		uint64_t pci_msi:4;
1684 		uint64_t reserved_44_44:1;
1685 		uint64_t twsi:1;
1686 		uint64_t rml:1;
1687 		uint64_t trace:1;
1688 		uint64_t gmx_drp:1;
1689 		uint64_t reserved_49_49:1;
1690 		uint64_t ipd_drp:1;
1691 		uint64_t reserved_51_51:1;
1692 		uint64_t timer:4;
1693 		uint64_t usb:1;
1694 		uint64_t pcm:1;
1695 		uint64_t mpi:1;
1696 		uint64_t twsi2:1;
1697 		uint64_t powiq:1;
1698 		uint64_t ipdppthr:1;
1699 		uint64_t reserved_62_62:1;
1700 		uint64_t bootdma:1;
1701 #endif
1702 	} cnf71xx;
1703 };
1704 
1705 union cvmx_ciu_intx_en0_w1c {
1706 	uint64_t u64;
1707 	struct cvmx_ciu_intx_en0_w1c_s {
1708 #ifdef __BIG_ENDIAN_BITFIELD
1709 		uint64_t bootdma:1;
1710 		uint64_t mii:1;
1711 		uint64_t ipdppthr:1;
1712 		uint64_t powiq:1;
1713 		uint64_t twsi2:1;
1714 		uint64_t mpi:1;
1715 		uint64_t pcm:1;
1716 		uint64_t usb:1;
1717 		uint64_t timer:4;
1718 		uint64_t key_zero:1;
1719 		uint64_t ipd_drp:1;
1720 		uint64_t gmx_drp:2;
1721 		uint64_t trace:1;
1722 		uint64_t rml:1;
1723 		uint64_t twsi:1;
1724 		uint64_t reserved_44_44:1;
1725 		uint64_t pci_msi:4;
1726 		uint64_t pci_int:4;
1727 		uint64_t uart:2;
1728 		uint64_t mbox:2;
1729 		uint64_t gpio:16;
1730 		uint64_t workq:16;
1731 #else
1732 		uint64_t workq:16;
1733 		uint64_t gpio:16;
1734 		uint64_t mbox:2;
1735 		uint64_t uart:2;
1736 		uint64_t pci_int:4;
1737 		uint64_t pci_msi:4;
1738 		uint64_t reserved_44_44:1;
1739 		uint64_t twsi:1;
1740 		uint64_t rml:1;
1741 		uint64_t trace:1;
1742 		uint64_t gmx_drp:2;
1743 		uint64_t ipd_drp:1;
1744 		uint64_t key_zero:1;
1745 		uint64_t timer:4;
1746 		uint64_t usb:1;
1747 		uint64_t pcm:1;
1748 		uint64_t mpi:1;
1749 		uint64_t twsi2:1;
1750 		uint64_t powiq:1;
1751 		uint64_t ipdppthr:1;
1752 		uint64_t mii:1;
1753 		uint64_t bootdma:1;
1754 #endif
1755 	} s;
1756 	struct cvmx_ciu_intx_en0_w1c_cn52xx {
1757 #ifdef __BIG_ENDIAN_BITFIELD
1758 		uint64_t bootdma:1;
1759 		uint64_t mii:1;
1760 		uint64_t ipdppthr:1;
1761 		uint64_t powiq:1;
1762 		uint64_t twsi2:1;
1763 		uint64_t reserved_57_58:2;
1764 		uint64_t usb:1;
1765 		uint64_t timer:4;
1766 		uint64_t reserved_51_51:1;
1767 		uint64_t ipd_drp:1;
1768 		uint64_t reserved_49_49:1;
1769 		uint64_t gmx_drp:1;
1770 		uint64_t trace:1;
1771 		uint64_t rml:1;
1772 		uint64_t twsi:1;
1773 		uint64_t reserved_44_44:1;
1774 		uint64_t pci_msi:4;
1775 		uint64_t pci_int:4;
1776 		uint64_t uart:2;
1777 		uint64_t mbox:2;
1778 		uint64_t gpio:16;
1779 		uint64_t workq:16;
1780 #else
1781 		uint64_t workq:16;
1782 		uint64_t gpio:16;
1783 		uint64_t mbox:2;
1784 		uint64_t uart:2;
1785 		uint64_t pci_int:4;
1786 		uint64_t pci_msi:4;
1787 		uint64_t reserved_44_44:1;
1788 		uint64_t twsi:1;
1789 		uint64_t rml:1;
1790 		uint64_t trace:1;
1791 		uint64_t gmx_drp:1;
1792 		uint64_t reserved_49_49:1;
1793 		uint64_t ipd_drp:1;
1794 		uint64_t reserved_51_51:1;
1795 		uint64_t timer:4;
1796 		uint64_t usb:1;
1797 		uint64_t reserved_57_58:2;
1798 		uint64_t twsi2:1;
1799 		uint64_t powiq:1;
1800 		uint64_t ipdppthr:1;
1801 		uint64_t mii:1;
1802 		uint64_t bootdma:1;
1803 #endif
1804 	} cn52xx;
1805 	struct cvmx_ciu_intx_en0_w1c_cn56xx {
1806 #ifdef __BIG_ENDIAN_BITFIELD
1807 		uint64_t bootdma:1;
1808 		uint64_t mii:1;
1809 		uint64_t ipdppthr:1;
1810 		uint64_t powiq:1;
1811 		uint64_t twsi2:1;
1812 		uint64_t reserved_57_58:2;
1813 		uint64_t usb:1;
1814 		uint64_t timer:4;
1815 		uint64_t key_zero:1;
1816 		uint64_t ipd_drp:1;
1817 		uint64_t gmx_drp:2;
1818 		uint64_t trace:1;
1819 		uint64_t rml:1;
1820 		uint64_t twsi:1;
1821 		uint64_t reserved_44_44:1;
1822 		uint64_t pci_msi:4;
1823 		uint64_t pci_int:4;
1824 		uint64_t uart:2;
1825 		uint64_t mbox:2;
1826 		uint64_t gpio:16;
1827 		uint64_t workq:16;
1828 #else
1829 		uint64_t workq:16;
1830 		uint64_t gpio:16;
1831 		uint64_t mbox:2;
1832 		uint64_t uart:2;
1833 		uint64_t pci_int:4;
1834 		uint64_t pci_msi:4;
1835 		uint64_t reserved_44_44:1;
1836 		uint64_t twsi:1;
1837 		uint64_t rml:1;
1838 		uint64_t trace:1;
1839 		uint64_t gmx_drp:2;
1840 		uint64_t ipd_drp:1;
1841 		uint64_t key_zero:1;
1842 		uint64_t timer:4;
1843 		uint64_t usb:1;
1844 		uint64_t reserved_57_58:2;
1845 		uint64_t twsi2:1;
1846 		uint64_t powiq:1;
1847 		uint64_t ipdppthr:1;
1848 		uint64_t mii:1;
1849 		uint64_t bootdma:1;
1850 #endif
1851 	} cn56xx;
1852 	struct cvmx_ciu_intx_en0_w1c_cn58xx {
1853 #ifdef __BIG_ENDIAN_BITFIELD
1854 		uint64_t reserved_56_63:8;
1855 		uint64_t timer:4;
1856 		uint64_t key_zero:1;
1857 		uint64_t ipd_drp:1;
1858 		uint64_t gmx_drp:2;
1859 		uint64_t trace:1;
1860 		uint64_t rml:1;
1861 		uint64_t twsi:1;
1862 		uint64_t reserved_44_44:1;
1863 		uint64_t pci_msi:4;
1864 		uint64_t pci_int:4;
1865 		uint64_t uart:2;
1866 		uint64_t mbox:2;
1867 		uint64_t gpio:16;
1868 		uint64_t workq:16;
1869 #else
1870 		uint64_t workq:16;
1871 		uint64_t gpio:16;
1872 		uint64_t mbox:2;
1873 		uint64_t uart:2;
1874 		uint64_t pci_int:4;
1875 		uint64_t pci_msi:4;
1876 		uint64_t reserved_44_44:1;
1877 		uint64_t twsi:1;
1878 		uint64_t rml:1;
1879 		uint64_t trace:1;
1880 		uint64_t gmx_drp:2;
1881 		uint64_t ipd_drp:1;
1882 		uint64_t key_zero:1;
1883 		uint64_t timer:4;
1884 		uint64_t reserved_56_63:8;
1885 #endif
1886 	} cn58xx;
1887 	struct cvmx_ciu_intx_en0_w1c_cn61xx {
1888 #ifdef __BIG_ENDIAN_BITFIELD
1889 		uint64_t bootdma:1;
1890 		uint64_t mii:1;
1891 		uint64_t ipdppthr:1;
1892 		uint64_t powiq:1;
1893 		uint64_t twsi2:1;
1894 		uint64_t mpi:1;
1895 		uint64_t pcm:1;
1896 		uint64_t usb:1;
1897 		uint64_t timer:4;
1898 		uint64_t reserved_51_51:1;
1899 		uint64_t ipd_drp:1;
1900 		uint64_t gmx_drp:2;
1901 		uint64_t trace:1;
1902 		uint64_t rml:1;
1903 		uint64_t twsi:1;
1904 		uint64_t reserved_44_44:1;
1905 		uint64_t pci_msi:4;
1906 		uint64_t pci_int:4;
1907 		uint64_t uart:2;
1908 		uint64_t mbox:2;
1909 		uint64_t gpio:16;
1910 		uint64_t workq:16;
1911 #else
1912 		uint64_t workq:16;
1913 		uint64_t gpio:16;
1914 		uint64_t mbox:2;
1915 		uint64_t uart:2;
1916 		uint64_t pci_int:4;
1917 		uint64_t pci_msi:4;
1918 		uint64_t reserved_44_44:1;
1919 		uint64_t twsi:1;
1920 		uint64_t rml:1;
1921 		uint64_t trace:1;
1922 		uint64_t gmx_drp:2;
1923 		uint64_t ipd_drp:1;
1924 		uint64_t reserved_51_51:1;
1925 		uint64_t timer:4;
1926 		uint64_t usb:1;
1927 		uint64_t pcm:1;
1928 		uint64_t mpi:1;
1929 		uint64_t twsi2:1;
1930 		uint64_t powiq:1;
1931 		uint64_t ipdppthr:1;
1932 		uint64_t mii:1;
1933 		uint64_t bootdma:1;
1934 #endif
1935 	} cn61xx;
1936 	struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
1937 	struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
1938 	struct cvmx_ciu_intx_en0_w1c_cn66xx {
1939 #ifdef __BIG_ENDIAN_BITFIELD
1940 		uint64_t bootdma:1;
1941 		uint64_t mii:1;
1942 		uint64_t ipdppthr:1;
1943 		uint64_t powiq:1;
1944 		uint64_t twsi2:1;
1945 		uint64_t mpi:1;
1946 		uint64_t reserved_57_57:1;
1947 		uint64_t usb:1;
1948 		uint64_t timer:4;
1949 		uint64_t reserved_51_51:1;
1950 		uint64_t ipd_drp:1;
1951 		uint64_t gmx_drp:2;
1952 		uint64_t trace:1;
1953 		uint64_t rml:1;
1954 		uint64_t twsi:1;
1955 		uint64_t reserved_44_44:1;
1956 		uint64_t pci_msi:4;
1957 		uint64_t pci_int:4;
1958 		uint64_t uart:2;
1959 		uint64_t mbox:2;
1960 		uint64_t gpio:16;
1961 		uint64_t workq:16;
1962 #else
1963 		uint64_t workq:16;
1964 		uint64_t gpio:16;
1965 		uint64_t mbox:2;
1966 		uint64_t uart:2;
1967 		uint64_t pci_int:4;
1968 		uint64_t pci_msi:4;
1969 		uint64_t reserved_44_44:1;
1970 		uint64_t twsi:1;
1971 		uint64_t rml:1;
1972 		uint64_t trace:1;
1973 		uint64_t gmx_drp:2;
1974 		uint64_t ipd_drp:1;
1975 		uint64_t reserved_51_51:1;
1976 		uint64_t timer:4;
1977 		uint64_t usb:1;
1978 		uint64_t reserved_57_57:1;
1979 		uint64_t mpi:1;
1980 		uint64_t twsi2:1;
1981 		uint64_t powiq:1;
1982 		uint64_t ipdppthr:1;
1983 		uint64_t mii:1;
1984 		uint64_t bootdma:1;
1985 #endif
1986 	} cn66xx;
1987 	struct cvmx_ciu_intx_en0_w1c_cnf71xx {
1988 #ifdef __BIG_ENDIAN_BITFIELD
1989 		uint64_t bootdma:1;
1990 		uint64_t reserved_62_62:1;
1991 		uint64_t ipdppthr:1;
1992 		uint64_t powiq:1;
1993 		uint64_t twsi2:1;
1994 		uint64_t mpi:1;
1995 		uint64_t pcm:1;
1996 		uint64_t usb:1;
1997 		uint64_t timer:4;
1998 		uint64_t reserved_51_51:1;
1999 		uint64_t ipd_drp:1;
2000 		uint64_t reserved_49_49:1;
2001 		uint64_t gmx_drp:1;
2002 		uint64_t trace:1;
2003 		uint64_t rml:1;
2004 		uint64_t twsi:1;
2005 		uint64_t reserved_44_44:1;
2006 		uint64_t pci_msi:4;
2007 		uint64_t pci_int:4;
2008 		uint64_t uart:2;
2009 		uint64_t mbox:2;
2010 		uint64_t gpio:16;
2011 		uint64_t workq:16;
2012 #else
2013 		uint64_t workq:16;
2014 		uint64_t gpio:16;
2015 		uint64_t mbox:2;
2016 		uint64_t uart:2;
2017 		uint64_t pci_int:4;
2018 		uint64_t pci_msi:4;
2019 		uint64_t reserved_44_44:1;
2020 		uint64_t twsi:1;
2021 		uint64_t rml:1;
2022 		uint64_t trace:1;
2023 		uint64_t gmx_drp:1;
2024 		uint64_t reserved_49_49:1;
2025 		uint64_t ipd_drp:1;
2026 		uint64_t reserved_51_51:1;
2027 		uint64_t timer:4;
2028 		uint64_t usb:1;
2029 		uint64_t pcm:1;
2030 		uint64_t mpi:1;
2031 		uint64_t twsi2:1;
2032 		uint64_t powiq:1;
2033 		uint64_t ipdppthr:1;
2034 		uint64_t reserved_62_62:1;
2035 		uint64_t bootdma:1;
2036 #endif
2037 	} cnf71xx;
2038 };
2039 
2040 union cvmx_ciu_intx_en0_w1s {
2041 	uint64_t u64;
2042 	struct cvmx_ciu_intx_en0_w1s_s {
2043 #ifdef __BIG_ENDIAN_BITFIELD
2044 		uint64_t bootdma:1;
2045 		uint64_t mii:1;
2046 		uint64_t ipdppthr:1;
2047 		uint64_t powiq:1;
2048 		uint64_t twsi2:1;
2049 		uint64_t mpi:1;
2050 		uint64_t pcm:1;
2051 		uint64_t usb:1;
2052 		uint64_t timer:4;
2053 		uint64_t key_zero:1;
2054 		uint64_t ipd_drp:1;
2055 		uint64_t gmx_drp:2;
2056 		uint64_t trace:1;
2057 		uint64_t rml:1;
2058 		uint64_t twsi:1;
2059 		uint64_t reserved_44_44:1;
2060 		uint64_t pci_msi:4;
2061 		uint64_t pci_int:4;
2062 		uint64_t uart:2;
2063 		uint64_t mbox:2;
2064 		uint64_t gpio:16;
2065 		uint64_t workq:16;
2066 #else
2067 		uint64_t workq:16;
2068 		uint64_t gpio:16;
2069 		uint64_t mbox:2;
2070 		uint64_t uart:2;
2071 		uint64_t pci_int:4;
2072 		uint64_t pci_msi:4;
2073 		uint64_t reserved_44_44:1;
2074 		uint64_t twsi:1;
2075 		uint64_t rml:1;
2076 		uint64_t trace:1;
2077 		uint64_t gmx_drp:2;
2078 		uint64_t ipd_drp:1;
2079 		uint64_t key_zero:1;
2080 		uint64_t timer:4;
2081 		uint64_t usb:1;
2082 		uint64_t pcm:1;
2083 		uint64_t mpi:1;
2084 		uint64_t twsi2:1;
2085 		uint64_t powiq:1;
2086 		uint64_t ipdppthr:1;
2087 		uint64_t mii:1;
2088 		uint64_t bootdma:1;
2089 #endif
2090 	} s;
2091 	struct cvmx_ciu_intx_en0_w1s_cn52xx {
2092 #ifdef __BIG_ENDIAN_BITFIELD
2093 		uint64_t bootdma:1;
2094 		uint64_t mii:1;
2095 		uint64_t ipdppthr:1;
2096 		uint64_t powiq:1;
2097 		uint64_t twsi2:1;
2098 		uint64_t reserved_57_58:2;
2099 		uint64_t usb:1;
2100 		uint64_t timer:4;
2101 		uint64_t reserved_51_51:1;
2102 		uint64_t ipd_drp:1;
2103 		uint64_t reserved_49_49:1;
2104 		uint64_t gmx_drp:1;
2105 		uint64_t trace:1;
2106 		uint64_t rml:1;
2107 		uint64_t twsi:1;
2108 		uint64_t reserved_44_44:1;
2109 		uint64_t pci_msi:4;
2110 		uint64_t pci_int:4;
2111 		uint64_t uart:2;
2112 		uint64_t mbox:2;
2113 		uint64_t gpio:16;
2114 		uint64_t workq:16;
2115 #else
2116 		uint64_t workq:16;
2117 		uint64_t gpio:16;
2118 		uint64_t mbox:2;
2119 		uint64_t uart:2;
2120 		uint64_t pci_int:4;
2121 		uint64_t pci_msi:4;
2122 		uint64_t reserved_44_44:1;
2123 		uint64_t twsi:1;
2124 		uint64_t rml:1;
2125 		uint64_t trace:1;
2126 		uint64_t gmx_drp:1;
2127 		uint64_t reserved_49_49:1;
2128 		uint64_t ipd_drp:1;
2129 		uint64_t reserved_51_51:1;
2130 		uint64_t timer:4;
2131 		uint64_t usb:1;
2132 		uint64_t reserved_57_58:2;
2133 		uint64_t twsi2:1;
2134 		uint64_t powiq:1;
2135 		uint64_t ipdppthr:1;
2136 		uint64_t mii:1;
2137 		uint64_t bootdma:1;
2138 #endif
2139 	} cn52xx;
2140 	struct cvmx_ciu_intx_en0_w1s_cn56xx {
2141 #ifdef __BIG_ENDIAN_BITFIELD
2142 		uint64_t bootdma:1;
2143 		uint64_t mii:1;
2144 		uint64_t ipdppthr:1;
2145 		uint64_t powiq:1;
2146 		uint64_t twsi2:1;
2147 		uint64_t reserved_57_58:2;
2148 		uint64_t usb:1;
2149 		uint64_t timer:4;
2150 		uint64_t key_zero:1;
2151 		uint64_t ipd_drp:1;
2152 		uint64_t gmx_drp:2;
2153 		uint64_t trace:1;
2154 		uint64_t rml:1;
2155 		uint64_t twsi:1;
2156 		uint64_t reserved_44_44:1;
2157 		uint64_t pci_msi:4;
2158 		uint64_t pci_int:4;
2159 		uint64_t uart:2;
2160 		uint64_t mbox:2;
2161 		uint64_t gpio:16;
2162 		uint64_t workq:16;
2163 #else
2164 		uint64_t workq:16;
2165 		uint64_t gpio:16;
2166 		uint64_t mbox:2;
2167 		uint64_t uart:2;
2168 		uint64_t pci_int:4;
2169 		uint64_t pci_msi:4;
2170 		uint64_t reserved_44_44:1;
2171 		uint64_t twsi:1;
2172 		uint64_t rml:1;
2173 		uint64_t trace:1;
2174 		uint64_t gmx_drp:2;
2175 		uint64_t ipd_drp:1;
2176 		uint64_t key_zero:1;
2177 		uint64_t timer:4;
2178 		uint64_t usb:1;
2179 		uint64_t reserved_57_58:2;
2180 		uint64_t twsi2:1;
2181 		uint64_t powiq:1;
2182 		uint64_t ipdppthr:1;
2183 		uint64_t mii:1;
2184 		uint64_t bootdma:1;
2185 #endif
2186 	} cn56xx;
2187 	struct cvmx_ciu_intx_en0_w1s_cn58xx {
2188 #ifdef __BIG_ENDIAN_BITFIELD
2189 		uint64_t reserved_56_63:8;
2190 		uint64_t timer:4;
2191 		uint64_t key_zero:1;
2192 		uint64_t ipd_drp:1;
2193 		uint64_t gmx_drp:2;
2194 		uint64_t trace:1;
2195 		uint64_t rml:1;
2196 		uint64_t twsi:1;
2197 		uint64_t reserved_44_44:1;
2198 		uint64_t pci_msi:4;
2199 		uint64_t pci_int:4;
2200 		uint64_t uart:2;
2201 		uint64_t mbox:2;
2202 		uint64_t gpio:16;
2203 		uint64_t workq:16;
2204 #else
2205 		uint64_t workq:16;
2206 		uint64_t gpio:16;
2207 		uint64_t mbox:2;
2208 		uint64_t uart:2;
2209 		uint64_t pci_int:4;
2210 		uint64_t pci_msi:4;
2211 		uint64_t reserved_44_44:1;
2212 		uint64_t twsi:1;
2213 		uint64_t rml:1;
2214 		uint64_t trace:1;
2215 		uint64_t gmx_drp:2;
2216 		uint64_t ipd_drp:1;
2217 		uint64_t key_zero:1;
2218 		uint64_t timer:4;
2219 		uint64_t reserved_56_63:8;
2220 #endif
2221 	} cn58xx;
2222 	struct cvmx_ciu_intx_en0_w1s_cn61xx {
2223 #ifdef __BIG_ENDIAN_BITFIELD
2224 		uint64_t bootdma:1;
2225 		uint64_t mii:1;
2226 		uint64_t ipdppthr:1;
2227 		uint64_t powiq:1;
2228 		uint64_t twsi2:1;
2229 		uint64_t mpi:1;
2230 		uint64_t pcm:1;
2231 		uint64_t usb:1;
2232 		uint64_t timer:4;
2233 		uint64_t reserved_51_51:1;
2234 		uint64_t ipd_drp:1;
2235 		uint64_t gmx_drp:2;
2236 		uint64_t trace:1;
2237 		uint64_t rml:1;
2238 		uint64_t twsi:1;
2239 		uint64_t reserved_44_44:1;
2240 		uint64_t pci_msi:4;
2241 		uint64_t pci_int:4;
2242 		uint64_t uart:2;
2243 		uint64_t mbox:2;
2244 		uint64_t gpio:16;
2245 		uint64_t workq:16;
2246 #else
2247 		uint64_t workq:16;
2248 		uint64_t gpio:16;
2249 		uint64_t mbox:2;
2250 		uint64_t uart:2;
2251 		uint64_t pci_int:4;
2252 		uint64_t pci_msi:4;
2253 		uint64_t reserved_44_44:1;
2254 		uint64_t twsi:1;
2255 		uint64_t rml:1;
2256 		uint64_t trace:1;
2257 		uint64_t gmx_drp:2;
2258 		uint64_t ipd_drp:1;
2259 		uint64_t reserved_51_51:1;
2260 		uint64_t timer:4;
2261 		uint64_t usb:1;
2262 		uint64_t pcm:1;
2263 		uint64_t mpi:1;
2264 		uint64_t twsi2:1;
2265 		uint64_t powiq:1;
2266 		uint64_t ipdppthr:1;
2267 		uint64_t mii:1;
2268 		uint64_t bootdma:1;
2269 #endif
2270 	} cn61xx;
2271 	struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
2272 	struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
2273 	struct cvmx_ciu_intx_en0_w1s_cn66xx {
2274 #ifdef __BIG_ENDIAN_BITFIELD
2275 		uint64_t bootdma:1;
2276 		uint64_t mii:1;
2277 		uint64_t ipdppthr:1;
2278 		uint64_t powiq:1;
2279 		uint64_t twsi2:1;
2280 		uint64_t mpi:1;
2281 		uint64_t reserved_57_57:1;
2282 		uint64_t usb:1;
2283 		uint64_t timer:4;
2284 		uint64_t reserved_51_51:1;
2285 		uint64_t ipd_drp:1;
2286 		uint64_t gmx_drp:2;
2287 		uint64_t trace:1;
2288 		uint64_t rml:1;
2289 		uint64_t twsi:1;
2290 		uint64_t reserved_44_44:1;
2291 		uint64_t pci_msi:4;
2292 		uint64_t pci_int:4;
2293 		uint64_t uart:2;
2294 		uint64_t mbox:2;
2295 		uint64_t gpio:16;
2296 		uint64_t workq:16;
2297 #else
2298 		uint64_t workq:16;
2299 		uint64_t gpio:16;
2300 		uint64_t mbox:2;
2301 		uint64_t uart:2;
2302 		uint64_t pci_int:4;
2303 		uint64_t pci_msi:4;
2304 		uint64_t reserved_44_44:1;
2305 		uint64_t twsi:1;
2306 		uint64_t rml:1;
2307 		uint64_t trace:1;
2308 		uint64_t gmx_drp:2;
2309 		uint64_t ipd_drp:1;
2310 		uint64_t reserved_51_51:1;
2311 		uint64_t timer:4;
2312 		uint64_t usb:1;
2313 		uint64_t reserved_57_57:1;
2314 		uint64_t mpi:1;
2315 		uint64_t twsi2:1;
2316 		uint64_t powiq:1;
2317 		uint64_t ipdppthr:1;
2318 		uint64_t mii:1;
2319 		uint64_t bootdma:1;
2320 #endif
2321 	} cn66xx;
2322 	struct cvmx_ciu_intx_en0_w1s_cnf71xx {
2323 #ifdef __BIG_ENDIAN_BITFIELD
2324 		uint64_t bootdma:1;
2325 		uint64_t reserved_62_62:1;
2326 		uint64_t ipdppthr:1;
2327 		uint64_t powiq:1;
2328 		uint64_t twsi2:1;
2329 		uint64_t mpi:1;
2330 		uint64_t pcm:1;
2331 		uint64_t usb:1;
2332 		uint64_t timer:4;
2333 		uint64_t reserved_51_51:1;
2334 		uint64_t ipd_drp:1;
2335 		uint64_t reserved_49_49:1;
2336 		uint64_t gmx_drp:1;
2337 		uint64_t trace:1;
2338 		uint64_t rml:1;
2339 		uint64_t twsi:1;
2340 		uint64_t reserved_44_44:1;
2341 		uint64_t pci_msi:4;
2342 		uint64_t pci_int:4;
2343 		uint64_t uart:2;
2344 		uint64_t mbox:2;
2345 		uint64_t gpio:16;
2346 		uint64_t workq:16;
2347 #else
2348 		uint64_t workq:16;
2349 		uint64_t gpio:16;
2350 		uint64_t mbox:2;
2351 		uint64_t uart:2;
2352 		uint64_t pci_int:4;
2353 		uint64_t pci_msi:4;
2354 		uint64_t reserved_44_44:1;
2355 		uint64_t twsi:1;
2356 		uint64_t rml:1;
2357 		uint64_t trace:1;
2358 		uint64_t gmx_drp:1;
2359 		uint64_t reserved_49_49:1;
2360 		uint64_t ipd_drp:1;
2361 		uint64_t reserved_51_51:1;
2362 		uint64_t timer:4;
2363 		uint64_t usb:1;
2364 		uint64_t pcm:1;
2365 		uint64_t mpi:1;
2366 		uint64_t twsi2:1;
2367 		uint64_t powiq:1;
2368 		uint64_t ipdppthr:1;
2369 		uint64_t reserved_62_62:1;
2370 		uint64_t bootdma:1;
2371 #endif
2372 	} cnf71xx;
2373 };
2374 
2375 union cvmx_ciu_intx_en1 {
2376 	uint64_t u64;
2377 	struct cvmx_ciu_intx_en1_s {
2378 #ifdef __BIG_ENDIAN_BITFIELD
2379 		uint64_t rst:1;
2380 		uint64_t reserved_62_62:1;
2381 		uint64_t srio3:1;
2382 		uint64_t srio2:1;
2383 		uint64_t reserved_57_59:3;
2384 		uint64_t dfm:1;
2385 		uint64_t reserved_53_55:3;
2386 		uint64_t lmc0:1;
2387 		uint64_t srio1:1;
2388 		uint64_t srio0:1;
2389 		uint64_t pem1:1;
2390 		uint64_t pem0:1;
2391 		uint64_t ptp:1;
2392 		uint64_t agl:1;
2393 		uint64_t reserved_41_45:5;
2394 		uint64_t dpi_dma:1;
2395 		uint64_t reserved_38_39:2;
2396 		uint64_t agx1:1;
2397 		uint64_t agx0:1;
2398 		uint64_t dpi:1;
2399 		uint64_t sli:1;
2400 		uint64_t usb:1;
2401 		uint64_t dfa:1;
2402 		uint64_t key:1;
2403 		uint64_t rad:1;
2404 		uint64_t tim:1;
2405 		uint64_t zip:1;
2406 		uint64_t pko:1;
2407 		uint64_t pip:1;
2408 		uint64_t ipd:1;
2409 		uint64_t l2c:1;
2410 		uint64_t pow:1;
2411 		uint64_t fpa:1;
2412 		uint64_t iob:1;
2413 		uint64_t mio:1;
2414 		uint64_t nand:1;
2415 		uint64_t mii1:1;
2416 		uint64_t usb1:1;
2417 		uint64_t uart2:1;
2418 		uint64_t wdog:16;
2419 #else
2420 		uint64_t wdog:16;
2421 		uint64_t uart2:1;
2422 		uint64_t usb1:1;
2423 		uint64_t mii1:1;
2424 		uint64_t nand:1;
2425 		uint64_t mio:1;
2426 		uint64_t iob:1;
2427 		uint64_t fpa:1;
2428 		uint64_t pow:1;
2429 		uint64_t l2c:1;
2430 		uint64_t ipd:1;
2431 		uint64_t pip:1;
2432 		uint64_t pko:1;
2433 		uint64_t zip:1;
2434 		uint64_t tim:1;
2435 		uint64_t rad:1;
2436 		uint64_t key:1;
2437 		uint64_t dfa:1;
2438 		uint64_t usb:1;
2439 		uint64_t sli:1;
2440 		uint64_t dpi:1;
2441 		uint64_t agx0:1;
2442 		uint64_t agx1:1;
2443 		uint64_t reserved_38_39:2;
2444 		uint64_t dpi_dma:1;
2445 		uint64_t reserved_41_45:5;
2446 		uint64_t agl:1;
2447 		uint64_t ptp:1;
2448 		uint64_t pem0:1;
2449 		uint64_t pem1:1;
2450 		uint64_t srio0:1;
2451 		uint64_t srio1:1;
2452 		uint64_t lmc0:1;
2453 		uint64_t reserved_53_55:3;
2454 		uint64_t dfm:1;
2455 		uint64_t reserved_57_59:3;
2456 		uint64_t srio2:1;
2457 		uint64_t srio3:1;
2458 		uint64_t reserved_62_62:1;
2459 		uint64_t rst:1;
2460 #endif
2461 	} s;
2462 	struct cvmx_ciu_intx_en1_cn30xx {
2463 #ifdef __BIG_ENDIAN_BITFIELD
2464 		uint64_t reserved_1_63:63;
2465 		uint64_t wdog:1;
2466 #else
2467 		uint64_t wdog:1;
2468 		uint64_t reserved_1_63:63;
2469 #endif
2470 	} cn30xx;
2471 	struct cvmx_ciu_intx_en1_cn31xx {
2472 #ifdef __BIG_ENDIAN_BITFIELD
2473 		uint64_t reserved_2_63:62;
2474 		uint64_t wdog:2;
2475 #else
2476 		uint64_t wdog:2;
2477 		uint64_t reserved_2_63:62;
2478 #endif
2479 	} cn31xx;
2480 	struct cvmx_ciu_intx_en1_cn38xx {
2481 #ifdef __BIG_ENDIAN_BITFIELD
2482 		uint64_t reserved_16_63:48;
2483 		uint64_t wdog:16;
2484 #else
2485 		uint64_t wdog:16;
2486 		uint64_t reserved_16_63:48;
2487 #endif
2488 	} cn38xx;
2489 	struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
2490 	struct cvmx_ciu_intx_en1_cn31xx cn50xx;
2491 	struct cvmx_ciu_intx_en1_cn52xx {
2492 #ifdef __BIG_ENDIAN_BITFIELD
2493 		uint64_t reserved_20_63:44;
2494 		uint64_t nand:1;
2495 		uint64_t mii1:1;
2496 		uint64_t usb1:1;
2497 		uint64_t uart2:1;
2498 		uint64_t reserved_4_15:12;
2499 		uint64_t wdog:4;
2500 #else
2501 		uint64_t wdog:4;
2502 		uint64_t reserved_4_15:12;
2503 		uint64_t uart2:1;
2504 		uint64_t usb1:1;
2505 		uint64_t mii1:1;
2506 		uint64_t nand:1;
2507 		uint64_t reserved_20_63:44;
2508 #endif
2509 	} cn52xx;
2510 	struct cvmx_ciu_intx_en1_cn52xxp1 {
2511 #ifdef __BIG_ENDIAN_BITFIELD
2512 		uint64_t reserved_19_63:45;
2513 		uint64_t mii1:1;
2514 		uint64_t usb1:1;
2515 		uint64_t uart2:1;
2516 		uint64_t reserved_4_15:12;
2517 		uint64_t wdog:4;
2518 #else
2519 		uint64_t wdog:4;
2520 		uint64_t reserved_4_15:12;
2521 		uint64_t uart2:1;
2522 		uint64_t usb1:1;
2523 		uint64_t mii1:1;
2524 		uint64_t reserved_19_63:45;
2525 #endif
2526 	} cn52xxp1;
2527 	struct cvmx_ciu_intx_en1_cn56xx {
2528 #ifdef __BIG_ENDIAN_BITFIELD
2529 		uint64_t reserved_12_63:52;
2530 		uint64_t wdog:12;
2531 #else
2532 		uint64_t wdog:12;
2533 		uint64_t reserved_12_63:52;
2534 #endif
2535 	} cn56xx;
2536 	struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
2537 	struct cvmx_ciu_intx_en1_cn38xx cn58xx;
2538 	struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
2539 	struct cvmx_ciu_intx_en1_cn61xx {
2540 #ifdef __BIG_ENDIAN_BITFIELD
2541 		uint64_t rst:1;
2542 		uint64_t reserved_53_62:10;
2543 		uint64_t lmc0:1;
2544 		uint64_t reserved_50_51:2;
2545 		uint64_t pem1:1;
2546 		uint64_t pem0:1;
2547 		uint64_t ptp:1;
2548 		uint64_t agl:1;
2549 		uint64_t reserved_41_45:5;
2550 		uint64_t dpi_dma:1;
2551 		uint64_t reserved_38_39:2;
2552 		uint64_t agx1:1;
2553 		uint64_t agx0:1;
2554 		uint64_t dpi:1;
2555 		uint64_t sli:1;
2556 		uint64_t usb:1;
2557 		uint64_t dfa:1;
2558 		uint64_t key:1;
2559 		uint64_t rad:1;
2560 		uint64_t tim:1;
2561 		uint64_t zip:1;
2562 		uint64_t pko:1;
2563 		uint64_t pip:1;
2564 		uint64_t ipd:1;
2565 		uint64_t l2c:1;
2566 		uint64_t pow:1;
2567 		uint64_t fpa:1;
2568 		uint64_t iob:1;
2569 		uint64_t mio:1;
2570 		uint64_t nand:1;
2571 		uint64_t mii1:1;
2572 		uint64_t reserved_4_17:14;
2573 		uint64_t wdog:4;
2574 #else
2575 		uint64_t wdog:4;
2576 		uint64_t reserved_4_17:14;
2577 		uint64_t mii1:1;
2578 		uint64_t nand:1;
2579 		uint64_t mio:1;
2580 		uint64_t iob:1;
2581 		uint64_t fpa:1;
2582 		uint64_t pow:1;
2583 		uint64_t l2c:1;
2584 		uint64_t ipd:1;
2585 		uint64_t pip:1;
2586 		uint64_t pko:1;
2587 		uint64_t zip:1;
2588 		uint64_t tim:1;
2589 		uint64_t rad:1;
2590 		uint64_t key:1;
2591 		uint64_t dfa:1;
2592 		uint64_t usb:1;
2593 		uint64_t sli:1;
2594 		uint64_t dpi:1;
2595 		uint64_t agx0:1;
2596 		uint64_t agx1:1;
2597 		uint64_t reserved_38_39:2;
2598 		uint64_t dpi_dma:1;
2599 		uint64_t reserved_41_45:5;
2600 		uint64_t agl:1;
2601 		uint64_t ptp:1;
2602 		uint64_t pem0:1;
2603 		uint64_t pem1:1;
2604 		uint64_t reserved_50_51:2;
2605 		uint64_t lmc0:1;
2606 		uint64_t reserved_53_62:10;
2607 		uint64_t rst:1;
2608 #endif
2609 	} cn61xx;
2610 	struct cvmx_ciu_intx_en1_cn63xx {
2611 #ifdef __BIG_ENDIAN_BITFIELD
2612 		uint64_t rst:1;
2613 		uint64_t reserved_57_62:6;
2614 		uint64_t dfm:1;
2615 		uint64_t reserved_53_55:3;
2616 		uint64_t lmc0:1;
2617 		uint64_t srio1:1;
2618 		uint64_t srio0:1;
2619 		uint64_t pem1:1;
2620 		uint64_t pem0:1;
2621 		uint64_t ptp:1;
2622 		uint64_t agl:1;
2623 		uint64_t reserved_37_45:9;
2624 		uint64_t agx0:1;
2625 		uint64_t dpi:1;
2626 		uint64_t sli:1;
2627 		uint64_t usb:1;
2628 		uint64_t dfa:1;
2629 		uint64_t key:1;
2630 		uint64_t rad:1;
2631 		uint64_t tim:1;
2632 		uint64_t zip:1;
2633 		uint64_t pko:1;
2634 		uint64_t pip:1;
2635 		uint64_t ipd:1;
2636 		uint64_t l2c:1;
2637 		uint64_t pow:1;
2638 		uint64_t fpa:1;
2639 		uint64_t iob:1;
2640 		uint64_t mio:1;
2641 		uint64_t nand:1;
2642 		uint64_t mii1:1;
2643 		uint64_t reserved_6_17:12;
2644 		uint64_t wdog:6;
2645 #else
2646 		uint64_t wdog:6;
2647 		uint64_t reserved_6_17:12;
2648 		uint64_t mii1:1;
2649 		uint64_t nand:1;
2650 		uint64_t mio:1;
2651 		uint64_t iob:1;
2652 		uint64_t fpa:1;
2653 		uint64_t pow:1;
2654 		uint64_t l2c:1;
2655 		uint64_t ipd:1;
2656 		uint64_t pip:1;
2657 		uint64_t pko:1;
2658 		uint64_t zip:1;
2659 		uint64_t tim:1;
2660 		uint64_t rad:1;
2661 		uint64_t key:1;
2662 		uint64_t dfa:1;
2663 		uint64_t usb:1;
2664 		uint64_t sli:1;
2665 		uint64_t dpi:1;
2666 		uint64_t agx0:1;
2667 		uint64_t reserved_37_45:9;
2668 		uint64_t agl:1;
2669 		uint64_t ptp:1;
2670 		uint64_t pem0:1;
2671 		uint64_t pem1:1;
2672 		uint64_t srio0:1;
2673 		uint64_t srio1:1;
2674 		uint64_t lmc0:1;
2675 		uint64_t reserved_53_55:3;
2676 		uint64_t dfm:1;
2677 		uint64_t reserved_57_62:6;
2678 		uint64_t rst:1;
2679 #endif
2680 	} cn63xx;
2681 	struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
2682 	struct cvmx_ciu_intx_en1_cn66xx {
2683 #ifdef __BIG_ENDIAN_BITFIELD
2684 		uint64_t rst:1;
2685 		uint64_t reserved_62_62:1;
2686 		uint64_t srio3:1;
2687 		uint64_t srio2:1;
2688 		uint64_t reserved_57_59:3;
2689 		uint64_t dfm:1;
2690 		uint64_t reserved_53_55:3;
2691 		uint64_t lmc0:1;
2692 		uint64_t reserved_51_51:1;
2693 		uint64_t srio0:1;
2694 		uint64_t pem1:1;
2695 		uint64_t pem0:1;
2696 		uint64_t ptp:1;
2697 		uint64_t agl:1;
2698 		uint64_t reserved_38_45:8;
2699 		uint64_t agx1:1;
2700 		uint64_t agx0:1;
2701 		uint64_t dpi:1;
2702 		uint64_t sli:1;
2703 		uint64_t usb:1;
2704 		uint64_t dfa:1;
2705 		uint64_t key:1;
2706 		uint64_t rad:1;
2707 		uint64_t tim:1;
2708 		uint64_t zip:1;
2709 		uint64_t pko:1;
2710 		uint64_t pip:1;
2711 		uint64_t ipd:1;
2712 		uint64_t l2c:1;
2713 		uint64_t pow:1;
2714 		uint64_t fpa:1;
2715 		uint64_t iob:1;
2716 		uint64_t mio:1;
2717 		uint64_t nand:1;
2718 		uint64_t mii1:1;
2719 		uint64_t reserved_10_17:8;
2720 		uint64_t wdog:10;
2721 #else
2722 		uint64_t wdog:10;
2723 		uint64_t reserved_10_17:8;
2724 		uint64_t mii1:1;
2725 		uint64_t nand:1;
2726 		uint64_t mio:1;
2727 		uint64_t iob:1;
2728 		uint64_t fpa:1;
2729 		uint64_t pow:1;
2730 		uint64_t l2c:1;
2731 		uint64_t ipd:1;
2732 		uint64_t pip:1;
2733 		uint64_t pko:1;
2734 		uint64_t zip:1;
2735 		uint64_t tim:1;
2736 		uint64_t rad:1;
2737 		uint64_t key:1;
2738 		uint64_t dfa:1;
2739 		uint64_t usb:1;
2740 		uint64_t sli:1;
2741 		uint64_t dpi:1;
2742 		uint64_t agx0:1;
2743 		uint64_t agx1:1;
2744 		uint64_t reserved_38_45:8;
2745 		uint64_t agl:1;
2746 		uint64_t ptp:1;
2747 		uint64_t pem0:1;
2748 		uint64_t pem1:1;
2749 		uint64_t srio0:1;
2750 		uint64_t reserved_51_51:1;
2751 		uint64_t lmc0:1;
2752 		uint64_t reserved_53_55:3;
2753 		uint64_t dfm:1;
2754 		uint64_t reserved_57_59:3;
2755 		uint64_t srio2:1;
2756 		uint64_t srio3:1;
2757 		uint64_t reserved_62_62:1;
2758 		uint64_t rst:1;
2759 #endif
2760 	} cn66xx;
2761 	struct cvmx_ciu_intx_en1_cnf71xx {
2762 #ifdef __BIG_ENDIAN_BITFIELD
2763 		uint64_t rst:1;
2764 		uint64_t reserved_53_62:10;
2765 		uint64_t lmc0:1;
2766 		uint64_t reserved_50_51:2;
2767 		uint64_t pem1:1;
2768 		uint64_t pem0:1;
2769 		uint64_t ptp:1;
2770 		uint64_t reserved_41_46:6;
2771 		uint64_t dpi_dma:1;
2772 		uint64_t reserved_37_39:3;
2773 		uint64_t agx0:1;
2774 		uint64_t dpi:1;
2775 		uint64_t sli:1;
2776 		uint64_t usb:1;
2777 		uint64_t reserved_32_32:1;
2778 		uint64_t key:1;
2779 		uint64_t rad:1;
2780 		uint64_t tim:1;
2781 		uint64_t reserved_28_28:1;
2782 		uint64_t pko:1;
2783 		uint64_t pip:1;
2784 		uint64_t ipd:1;
2785 		uint64_t l2c:1;
2786 		uint64_t pow:1;
2787 		uint64_t fpa:1;
2788 		uint64_t iob:1;
2789 		uint64_t mio:1;
2790 		uint64_t nand:1;
2791 		uint64_t reserved_4_18:15;
2792 		uint64_t wdog:4;
2793 #else
2794 		uint64_t wdog:4;
2795 		uint64_t reserved_4_18:15;
2796 		uint64_t nand:1;
2797 		uint64_t mio:1;
2798 		uint64_t iob:1;
2799 		uint64_t fpa:1;
2800 		uint64_t pow:1;
2801 		uint64_t l2c:1;
2802 		uint64_t ipd:1;
2803 		uint64_t pip:1;
2804 		uint64_t pko:1;
2805 		uint64_t reserved_28_28:1;
2806 		uint64_t tim:1;
2807 		uint64_t rad:1;
2808 		uint64_t key:1;
2809 		uint64_t reserved_32_32:1;
2810 		uint64_t usb:1;
2811 		uint64_t sli:1;
2812 		uint64_t dpi:1;
2813 		uint64_t agx0:1;
2814 		uint64_t reserved_37_39:3;
2815 		uint64_t dpi_dma:1;
2816 		uint64_t reserved_41_46:6;
2817 		uint64_t ptp:1;
2818 		uint64_t pem0:1;
2819 		uint64_t pem1:1;
2820 		uint64_t reserved_50_51:2;
2821 		uint64_t lmc0:1;
2822 		uint64_t reserved_53_62:10;
2823 		uint64_t rst:1;
2824 #endif
2825 	} cnf71xx;
2826 };
2827 
2828 union cvmx_ciu_intx_en1_w1c {
2829 	uint64_t u64;
2830 	struct cvmx_ciu_intx_en1_w1c_s {
2831 #ifdef __BIG_ENDIAN_BITFIELD
2832 		uint64_t rst:1;
2833 		uint64_t reserved_62_62:1;
2834 		uint64_t srio3:1;
2835 		uint64_t srio2:1;
2836 		uint64_t reserved_57_59:3;
2837 		uint64_t dfm:1;
2838 		uint64_t reserved_53_55:3;
2839 		uint64_t lmc0:1;
2840 		uint64_t srio1:1;
2841 		uint64_t srio0:1;
2842 		uint64_t pem1:1;
2843 		uint64_t pem0:1;
2844 		uint64_t ptp:1;
2845 		uint64_t agl:1;
2846 		uint64_t reserved_41_45:5;
2847 		uint64_t dpi_dma:1;
2848 		uint64_t reserved_38_39:2;
2849 		uint64_t agx1:1;
2850 		uint64_t agx0:1;
2851 		uint64_t dpi:1;
2852 		uint64_t sli:1;
2853 		uint64_t usb:1;
2854 		uint64_t dfa:1;
2855 		uint64_t key:1;
2856 		uint64_t rad:1;
2857 		uint64_t tim:1;
2858 		uint64_t zip:1;
2859 		uint64_t pko:1;
2860 		uint64_t pip:1;
2861 		uint64_t ipd:1;
2862 		uint64_t l2c:1;
2863 		uint64_t pow:1;
2864 		uint64_t fpa:1;
2865 		uint64_t iob:1;
2866 		uint64_t mio:1;
2867 		uint64_t nand:1;
2868 		uint64_t mii1:1;
2869 		uint64_t usb1:1;
2870 		uint64_t uart2:1;
2871 		uint64_t wdog:16;
2872 #else
2873 		uint64_t wdog:16;
2874 		uint64_t uart2:1;
2875 		uint64_t usb1:1;
2876 		uint64_t mii1:1;
2877 		uint64_t nand:1;
2878 		uint64_t mio:1;
2879 		uint64_t iob:1;
2880 		uint64_t fpa:1;
2881 		uint64_t pow:1;
2882 		uint64_t l2c:1;
2883 		uint64_t ipd:1;
2884 		uint64_t pip:1;
2885 		uint64_t pko:1;
2886 		uint64_t zip:1;
2887 		uint64_t tim:1;
2888 		uint64_t rad:1;
2889 		uint64_t key:1;
2890 		uint64_t dfa:1;
2891 		uint64_t usb:1;
2892 		uint64_t sli:1;
2893 		uint64_t dpi:1;
2894 		uint64_t agx0:1;
2895 		uint64_t agx1:1;
2896 		uint64_t reserved_38_39:2;
2897 		uint64_t dpi_dma:1;
2898 		uint64_t reserved_41_45:5;
2899 		uint64_t agl:1;
2900 		uint64_t ptp:1;
2901 		uint64_t pem0:1;
2902 		uint64_t pem1:1;
2903 		uint64_t srio0:1;
2904 		uint64_t srio1:1;
2905 		uint64_t lmc0:1;
2906 		uint64_t reserved_53_55:3;
2907 		uint64_t dfm:1;
2908 		uint64_t reserved_57_59:3;
2909 		uint64_t srio2:1;
2910 		uint64_t srio3:1;
2911 		uint64_t reserved_62_62:1;
2912 		uint64_t rst:1;
2913 #endif
2914 	} s;
2915 	struct cvmx_ciu_intx_en1_w1c_cn52xx {
2916 #ifdef __BIG_ENDIAN_BITFIELD
2917 		uint64_t reserved_20_63:44;
2918 		uint64_t nand:1;
2919 		uint64_t mii1:1;
2920 		uint64_t usb1:1;
2921 		uint64_t uart2:1;
2922 		uint64_t reserved_4_15:12;
2923 		uint64_t wdog:4;
2924 #else
2925 		uint64_t wdog:4;
2926 		uint64_t reserved_4_15:12;
2927 		uint64_t uart2:1;
2928 		uint64_t usb1:1;
2929 		uint64_t mii1:1;
2930 		uint64_t nand:1;
2931 		uint64_t reserved_20_63:44;
2932 #endif
2933 	} cn52xx;
2934 	struct cvmx_ciu_intx_en1_w1c_cn56xx {
2935 #ifdef __BIG_ENDIAN_BITFIELD
2936 		uint64_t reserved_12_63:52;
2937 		uint64_t wdog:12;
2938 #else
2939 		uint64_t wdog:12;
2940 		uint64_t reserved_12_63:52;
2941 #endif
2942 	} cn56xx;
2943 	struct cvmx_ciu_intx_en1_w1c_cn58xx {
2944 #ifdef __BIG_ENDIAN_BITFIELD
2945 		uint64_t reserved_16_63:48;
2946 		uint64_t wdog:16;
2947 #else
2948 		uint64_t wdog:16;
2949 		uint64_t reserved_16_63:48;
2950 #endif
2951 	} cn58xx;
2952 	struct cvmx_ciu_intx_en1_w1c_cn61xx {
2953 #ifdef __BIG_ENDIAN_BITFIELD
2954 		uint64_t rst:1;
2955 		uint64_t reserved_53_62:10;
2956 		uint64_t lmc0:1;
2957 		uint64_t reserved_50_51:2;
2958 		uint64_t pem1:1;
2959 		uint64_t pem0:1;
2960 		uint64_t ptp:1;
2961 		uint64_t agl:1;
2962 		uint64_t reserved_41_45:5;
2963 		uint64_t dpi_dma:1;
2964 		uint64_t reserved_38_39:2;
2965 		uint64_t agx1:1;
2966 		uint64_t agx0:1;
2967 		uint64_t dpi:1;
2968 		uint64_t sli:1;
2969 		uint64_t usb:1;
2970 		uint64_t dfa:1;
2971 		uint64_t key:1;
2972 		uint64_t rad:1;
2973 		uint64_t tim:1;
2974 		uint64_t zip:1;
2975 		uint64_t pko:1;
2976 		uint64_t pip:1;
2977 		uint64_t ipd:1;
2978 		uint64_t l2c:1;
2979 		uint64_t pow:1;
2980 		uint64_t fpa:1;
2981 		uint64_t iob:1;
2982 		uint64_t mio:1;
2983 		uint64_t nand:1;
2984 		uint64_t mii1:1;
2985 		uint64_t reserved_4_17:14;
2986 		uint64_t wdog:4;
2987 #else
2988 		uint64_t wdog:4;
2989 		uint64_t reserved_4_17:14;
2990 		uint64_t mii1:1;
2991 		uint64_t nand:1;
2992 		uint64_t mio:1;
2993 		uint64_t iob:1;
2994 		uint64_t fpa:1;
2995 		uint64_t pow:1;
2996 		uint64_t l2c:1;
2997 		uint64_t ipd:1;
2998 		uint64_t pip:1;
2999 		uint64_t pko:1;
3000 		uint64_t zip:1;
3001 		uint64_t tim:1;
3002 		uint64_t rad:1;
3003 		uint64_t key:1;
3004 		uint64_t dfa:1;
3005 		uint64_t usb:1;
3006 		uint64_t sli:1;
3007 		uint64_t dpi:1;
3008 		uint64_t agx0:1;
3009 		uint64_t agx1:1;
3010 		uint64_t reserved_38_39:2;
3011 		uint64_t dpi_dma:1;
3012 		uint64_t reserved_41_45:5;
3013 		uint64_t agl:1;
3014 		uint64_t ptp:1;
3015 		uint64_t pem0:1;
3016 		uint64_t pem1:1;
3017 		uint64_t reserved_50_51:2;
3018 		uint64_t lmc0:1;
3019 		uint64_t reserved_53_62:10;
3020 		uint64_t rst:1;
3021 #endif
3022 	} cn61xx;
3023 	struct cvmx_ciu_intx_en1_w1c_cn63xx {
3024 #ifdef __BIG_ENDIAN_BITFIELD
3025 		uint64_t rst:1;
3026 		uint64_t reserved_57_62:6;
3027 		uint64_t dfm:1;
3028 		uint64_t reserved_53_55:3;
3029 		uint64_t lmc0:1;
3030 		uint64_t srio1:1;
3031 		uint64_t srio0:1;
3032 		uint64_t pem1:1;
3033 		uint64_t pem0:1;
3034 		uint64_t ptp:1;
3035 		uint64_t agl:1;
3036 		uint64_t reserved_37_45:9;
3037 		uint64_t agx0:1;
3038 		uint64_t dpi:1;
3039 		uint64_t sli:1;
3040 		uint64_t usb:1;
3041 		uint64_t dfa:1;
3042 		uint64_t key:1;
3043 		uint64_t rad:1;
3044 		uint64_t tim:1;
3045 		uint64_t zip:1;
3046 		uint64_t pko:1;
3047 		uint64_t pip:1;
3048 		uint64_t ipd:1;
3049 		uint64_t l2c:1;
3050 		uint64_t pow:1;
3051 		uint64_t fpa:1;
3052 		uint64_t iob:1;
3053 		uint64_t mio:1;
3054 		uint64_t nand:1;
3055 		uint64_t mii1:1;
3056 		uint64_t reserved_6_17:12;
3057 		uint64_t wdog:6;
3058 #else
3059 		uint64_t wdog:6;
3060 		uint64_t reserved_6_17:12;
3061 		uint64_t mii1:1;
3062 		uint64_t nand:1;
3063 		uint64_t mio:1;
3064 		uint64_t iob:1;
3065 		uint64_t fpa:1;
3066 		uint64_t pow:1;
3067 		uint64_t l2c:1;
3068 		uint64_t ipd:1;
3069 		uint64_t pip:1;
3070 		uint64_t pko:1;
3071 		uint64_t zip:1;
3072 		uint64_t tim:1;
3073 		uint64_t rad:1;
3074 		uint64_t key:1;
3075 		uint64_t dfa:1;
3076 		uint64_t usb:1;
3077 		uint64_t sli:1;
3078 		uint64_t dpi:1;
3079 		uint64_t agx0:1;
3080 		uint64_t reserved_37_45:9;
3081 		uint64_t agl:1;
3082 		uint64_t ptp:1;
3083 		uint64_t pem0:1;
3084 		uint64_t pem1:1;
3085 		uint64_t srio0:1;
3086 		uint64_t srio1:1;
3087 		uint64_t lmc0:1;
3088 		uint64_t reserved_53_55:3;
3089 		uint64_t dfm:1;
3090 		uint64_t reserved_57_62:6;
3091 		uint64_t rst:1;
3092 #endif
3093 	} cn63xx;
3094 	struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
3095 	struct cvmx_ciu_intx_en1_w1c_cn66xx {
3096 #ifdef __BIG_ENDIAN_BITFIELD
3097 		uint64_t rst:1;
3098 		uint64_t reserved_62_62:1;
3099 		uint64_t srio3:1;
3100 		uint64_t srio2:1;
3101 		uint64_t reserved_57_59:3;
3102 		uint64_t dfm:1;
3103 		uint64_t reserved_53_55:3;
3104 		uint64_t lmc0:1;
3105 		uint64_t reserved_51_51:1;
3106 		uint64_t srio0:1;
3107 		uint64_t pem1:1;
3108 		uint64_t pem0:1;
3109 		uint64_t ptp:1;
3110 		uint64_t agl:1;
3111 		uint64_t reserved_38_45:8;
3112 		uint64_t agx1:1;
3113 		uint64_t agx0:1;
3114 		uint64_t dpi:1;
3115 		uint64_t sli:1;
3116 		uint64_t usb:1;
3117 		uint64_t dfa:1;
3118 		uint64_t key:1;
3119 		uint64_t rad:1;
3120 		uint64_t tim:1;
3121 		uint64_t zip:1;
3122 		uint64_t pko:1;
3123 		uint64_t pip:1;
3124 		uint64_t ipd:1;
3125 		uint64_t l2c:1;
3126 		uint64_t pow:1;
3127 		uint64_t fpa:1;
3128 		uint64_t iob:1;
3129 		uint64_t mio:1;
3130 		uint64_t nand:1;
3131 		uint64_t mii1:1;
3132 		uint64_t reserved_10_17:8;
3133 		uint64_t wdog:10;
3134 #else
3135 		uint64_t wdog:10;
3136 		uint64_t reserved_10_17:8;
3137 		uint64_t mii1:1;
3138 		uint64_t nand:1;
3139 		uint64_t mio:1;
3140 		uint64_t iob:1;
3141 		uint64_t fpa:1;
3142 		uint64_t pow:1;
3143 		uint64_t l2c:1;
3144 		uint64_t ipd:1;
3145 		uint64_t pip:1;
3146 		uint64_t pko:1;
3147 		uint64_t zip:1;
3148 		uint64_t tim:1;
3149 		uint64_t rad:1;
3150 		uint64_t key:1;
3151 		uint64_t dfa:1;
3152 		uint64_t usb:1;
3153 		uint64_t sli:1;
3154 		uint64_t dpi:1;
3155 		uint64_t agx0:1;
3156 		uint64_t agx1:1;
3157 		uint64_t reserved_38_45:8;
3158 		uint64_t agl:1;
3159 		uint64_t ptp:1;
3160 		uint64_t pem0:1;
3161 		uint64_t pem1:1;
3162 		uint64_t srio0:1;
3163 		uint64_t reserved_51_51:1;
3164 		uint64_t lmc0:1;
3165 		uint64_t reserved_53_55:3;
3166 		uint64_t dfm:1;
3167 		uint64_t reserved_57_59:3;
3168 		uint64_t srio2:1;
3169 		uint64_t srio3:1;
3170 		uint64_t reserved_62_62:1;
3171 		uint64_t rst:1;
3172 #endif
3173 	} cn66xx;
3174 	struct cvmx_ciu_intx_en1_w1c_cnf71xx {
3175 #ifdef __BIG_ENDIAN_BITFIELD
3176 		uint64_t rst:1;
3177 		uint64_t reserved_53_62:10;
3178 		uint64_t lmc0:1;
3179 		uint64_t reserved_50_51:2;
3180 		uint64_t pem1:1;
3181 		uint64_t pem0:1;
3182 		uint64_t ptp:1;
3183 		uint64_t reserved_41_46:6;
3184 		uint64_t dpi_dma:1;
3185 		uint64_t reserved_37_39:3;
3186 		uint64_t agx0:1;
3187 		uint64_t dpi:1;
3188 		uint64_t sli:1;
3189 		uint64_t usb:1;
3190 		uint64_t reserved_32_32:1;
3191 		uint64_t key:1;
3192 		uint64_t rad:1;
3193 		uint64_t tim:1;
3194 		uint64_t reserved_28_28:1;
3195 		uint64_t pko:1;
3196 		uint64_t pip:1;
3197 		uint64_t ipd:1;
3198 		uint64_t l2c:1;
3199 		uint64_t pow:1;
3200 		uint64_t fpa:1;
3201 		uint64_t iob:1;
3202 		uint64_t mio:1;
3203 		uint64_t nand:1;
3204 		uint64_t reserved_4_18:15;
3205 		uint64_t wdog:4;
3206 #else
3207 		uint64_t wdog:4;
3208 		uint64_t reserved_4_18:15;
3209 		uint64_t nand:1;
3210 		uint64_t mio:1;
3211 		uint64_t iob:1;
3212 		uint64_t fpa:1;
3213 		uint64_t pow:1;
3214 		uint64_t l2c:1;
3215 		uint64_t ipd:1;
3216 		uint64_t pip:1;
3217 		uint64_t pko:1;
3218 		uint64_t reserved_28_28:1;
3219 		uint64_t tim:1;
3220 		uint64_t rad:1;
3221 		uint64_t key:1;
3222 		uint64_t reserved_32_32:1;
3223 		uint64_t usb:1;
3224 		uint64_t sli:1;
3225 		uint64_t dpi:1;
3226 		uint64_t agx0:1;
3227 		uint64_t reserved_37_39:3;
3228 		uint64_t dpi_dma:1;
3229 		uint64_t reserved_41_46:6;
3230 		uint64_t ptp:1;
3231 		uint64_t pem0:1;
3232 		uint64_t pem1:1;
3233 		uint64_t reserved_50_51:2;
3234 		uint64_t lmc0:1;
3235 		uint64_t reserved_53_62:10;
3236 		uint64_t rst:1;
3237 #endif
3238 	} cnf71xx;
3239 };
3240 
3241 union cvmx_ciu_intx_en1_w1s {
3242 	uint64_t u64;
3243 	struct cvmx_ciu_intx_en1_w1s_s {
3244 #ifdef __BIG_ENDIAN_BITFIELD
3245 		uint64_t rst:1;
3246 		uint64_t reserved_62_62:1;
3247 		uint64_t srio3:1;
3248 		uint64_t srio2:1;
3249 		uint64_t reserved_57_59:3;
3250 		uint64_t dfm:1;
3251 		uint64_t reserved_53_55:3;
3252 		uint64_t lmc0:1;
3253 		uint64_t srio1:1;
3254 		uint64_t srio0:1;
3255 		uint64_t pem1:1;
3256 		uint64_t pem0:1;
3257 		uint64_t ptp:1;
3258 		uint64_t agl:1;
3259 		uint64_t reserved_41_45:5;
3260 		uint64_t dpi_dma:1;
3261 		uint64_t reserved_38_39:2;
3262 		uint64_t agx1:1;
3263 		uint64_t agx0:1;
3264 		uint64_t dpi:1;
3265 		uint64_t sli:1;
3266 		uint64_t usb:1;
3267 		uint64_t dfa:1;
3268 		uint64_t key:1;
3269 		uint64_t rad:1;
3270 		uint64_t tim:1;
3271 		uint64_t zip:1;
3272 		uint64_t pko:1;
3273 		uint64_t pip:1;
3274 		uint64_t ipd:1;
3275 		uint64_t l2c:1;
3276 		uint64_t pow:1;
3277 		uint64_t fpa:1;
3278 		uint64_t iob:1;
3279 		uint64_t mio:1;
3280 		uint64_t nand:1;
3281 		uint64_t mii1:1;
3282 		uint64_t usb1:1;
3283 		uint64_t uart2:1;
3284 		uint64_t wdog:16;
3285 #else
3286 		uint64_t wdog:16;
3287 		uint64_t uart2:1;
3288 		uint64_t usb1:1;
3289 		uint64_t mii1:1;
3290 		uint64_t nand:1;
3291 		uint64_t mio:1;
3292 		uint64_t iob:1;
3293 		uint64_t fpa:1;
3294 		uint64_t pow:1;
3295 		uint64_t l2c:1;
3296 		uint64_t ipd:1;
3297 		uint64_t pip:1;
3298 		uint64_t pko:1;
3299 		uint64_t zip:1;
3300 		uint64_t tim:1;
3301 		uint64_t rad:1;
3302 		uint64_t key:1;
3303 		uint64_t dfa:1;
3304 		uint64_t usb:1;
3305 		uint64_t sli:1;
3306 		uint64_t dpi:1;
3307 		uint64_t agx0:1;
3308 		uint64_t agx1:1;
3309 		uint64_t reserved_38_39:2;
3310 		uint64_t dpi_dma:1;
3311 		uint64_t reserved_41_45:5;
3312 		uint64_t agl:1;
3313 		uint64_t ptp:1;
3314 		uint64_t pem0:1;
3315 		uint64_t pem1:1;
3316 		uint64_t srio0:1;
3317 		uint64_t srio1:1;
3318 		uint64_t lmc0:1;
3319 		uint64_t reserved_53_55:3;
3320 		uint64_t dfm:1;
3321 		uint64_t reserved_57_59:3;
3322 		uint64_t srio2:1;
3323 		uint64_t srio3:1;
3324 		uint64_t reserved_62_62:1;
3325 		uint64_t rst:1;
3326 #endif
3327 	} s;
3328 	struct cvmx_ciu_intx_en1_w1s_cn52xx {
3329 #ifdef __BIG_ENDIAN_BITFIELD
3330 		uint64_t reserved_20_63:44;
3331 		uint64_t nand:1;
3332 		uint64_t mii1:1;
3333 		uint64_t usb1:1;
3334 		uint64_t uart2:1;
3335 		uint64_t reserved_4_15:12;
3336 		uint64_t wdog:4;
3337 #else
3338 		uint64_t wdog:4;
3339 		uint64_t reserved_4_15:12;
3340 		uint64_t uart2:1;
3341 		uint64_t usb1:1;
3342 		uint64_t mii1:1;
3343 		uint64_t nand:1;
3344 		uint64_t reserved_20_63:44;
3345 #endif
3346 	} cn52xx;
3347 	struct cvmx_ciu_intx_en1_w1s_cn56xx {
3348 #ifdef __BIG_ENDIAN_BITFIELD
3349 		uint64_t reserved_12_63:52;
3350 		uint64_t wdog:12;
3351 #else
3352 		uint64_t wdog:12;
3353 		uint64_t reserved_12_63:52;
3354 #endif
3355 	} cn56xx;
3356 	struct cvmx_ciu_intx_en1_w1s_cn58xx {
3357 #ifdef __BIG_ENDIAN_BITFIELD
3358 		uint64_t reserved_16_63:48;
3359 		uint64_t wdog:16;
3360 #else
3361 		uint64_t wdog:16;
3362 		uint64_t reserved_16_63:48;
3363 #endif
3364 	} cn58xx;
3365 	struct cvmx_ciu_intx_en1_w1s_cn61xx {
3366 #ifdef __BIG_ENDIAN_BITFIELD
3367 		uint64_t rst:1;
3368 		uint64_t reserved_53_62:10;
3369 		uint64_t lmc0:1;
3370 		uint64_t reserved_50_51:2;
3371 		uint64_t pem1:1;
3372 		uint64_t pem0:1;
3373 		uint64_t ptp:1;
3374 		uint64_t agl:1;
3375 		uint64_t reserved_41_45:5;
3376 		uint64_t dpi_dma:1;
3377 		uint64_t reserved_38_39:2;
3378 		uint64_t agx1:1;
3379 		uint64_t agx0:1;
3380 		uint64_t dpi:1;
3381 		uint64_t sli:1;
3382 		uint64_t usb:1;
3383 		uint64_t dfa:1;
3384 		uint64_t key:1;
3385 		uint64_t rad:1;
3386 		uint64_t tim:1;
3387 		uint64_t zip:1;
3388 		uint64_t pko:1;
3389 		uint64_t pip:1;
3390 		uint64_t ipd:1;
3391 		uint64_t l2c:1;
3392 		uint64_t pow:1;
3393 		uint64_t fpa:1;
3394 		uint64_t iob:1;
3395 		uint64_t mio:1;
3396 		uint64_t nand:1;
3397 		uint64_t mii1:1;
3398 		uint64_t reserved_4_17:14;
3399 		uint64_t wdog:4;
3400 #else
3401 		uint64_t wdog:4;
3402 		uint64_t reserved_4_17:14;
3403 		uint64_t mii1:1;
3404 		uint64_t nand:1;
3405 		uint64_t mio:1;
3406 		uint64_t iob:1;
3407 		uint64_t fpa:1;
3408 		uint64_t pow:1;
3409 		uint64_t l2c:1;
3410 		uint64_t ipd:1;
3411 		uint64_t pip:1;
3412 		uint64_t pko:1;
3413 		uint64_t zip:1;
3414 		uint64_t tim:1;
3415 		uint64_t rad:1;
3416 		uint64_t key:1;
3417 		uint64_t dfa:1;
3418 		uint64_t usb:1;
3419 		uint64_t sli:1;
3420 		uint64_t dpi:1;
3421 		uint64_t agx0:1;
3422 		uint64_t agx1:1;
3423 		uint64_t reserved_38_39:2;
3424 		uint64_t dpi_dma:1;
3425 		uint64_t reserved_41_45:5;
3426 		uint64_t agl:1;
3427 		uint64_t ptp:1;
3428 		uint64_t pem0:1;
3429 		uint64_t pem1:1;
3430 		uint64_t reserved_50_51:2;
3431 		uint64_t lmc0:1;
3432 		uint64_t reserved_53_62:10;
3433 		uint64_t rst:1;
3434 #endif
3435 	} cn61xx;
3436 	struct cvmx_ciu_intx_en1_w1s_cn63xx {
3437 #ifdef __BIG_ENDIAN_BITFIELD
3438 		uint64_t rst:1;
3439 		uint64_t reserved_57_62:6;
3440 		uint64_t dfm:1;
3441 		uint64_t reserved_53_55:3;
3442 		uint64_t lmc0:1;
3443 		uint64_t srio1:1;
3444 		uint64_t srio0:1;
3445 		uint64_t pem1:1;
3446 		uint64_t pem0:1;
3447 		uint64_t ptp:1;
3448 		uint64_t agl:1;
3449 		uint64_t reserved_37_45:9;
3450 		uint64_t agx0:1;
3451 		uint64_t dpi:1;
3452 		uint64_t sli:1;
3453 		uint64_t usb:1;
3454 		uint64_t dfa:1;
3455 		uint64_t key:1;
3456 		uint64_t rad:1;
3457 		uint64_t tim:1;
3458 		uint64_t zip:1;
3459 		uint64_t pko:1;
3460 		uint64_t pip:1;
3461 		uint64_t ipd:1;
3462 		uint64_t l2c:1;
3463 		uint64_t pow:1;
3464 		uint64_t fpa:1;
3465 		uint64_t iob:1;
3466 		uint64_t mio:1;
3467 		uint64_t nand:1;
3468 		uint64_t mii1:1;
3469 		uint64_t reserved_6_17:12;
3470 		uint64_t wdog:6;
3471 #else
3472 		uint64_t wdog:6;
3473 		uint64_t reserved_6_17:12;
3474 		uint64_t mii1:1;
3475 		uint64_t nand:1;
3476 		uint64_t mio:1;
3477 		uint64_t iob:1;
3478 		uint64_t fpa:1;
3479 		uint64_t pow:1;
3480 		uint64_t l2c:1;
3481 		uint64_t ipd:1;
3482 		uint64_t pip:1;
3483 		uint64_t pko:1;
3484 		uint64_t zip:1;
3485 		uint64_t tim:1;
3486 		uint64_t rad:1;
3487 		uint64_t key:1;
3488 		uint64_t dfa:1;
3489 		uint64_t usb:1;
3490 		uint64_t sli:1;
3491 		uint64_t dpi:1;
3492 		uint64_t agx0:1;
3493 		uint64_t reserved_37_45:9;
3494 		uint64_t agl:1;
3495 		uint64_t ptp:1;
3496 		uint64_t pem0:1;
3497 		uint64_t pem1:1;
3498 		uint64_t srio0:1;
3499 		uint64_t srio1:1;
3500 		uint64_t lmc0:1;
3501 		uint64_t reserved_53_55:3;
3502 		uint64_t dfm:1;
3503 		uint64_t reserved_57_62:6;
3504 		uint64_t rst:1;
3505 #endif
3506 	} cn63xx;
3507 	struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
3508 	struct cvmx_ciu_intx_en1_w1s_cn66xx {
3509 #ifdef __BIG_ENDIAN_BITFIELD
3510 		uint64_t rst:1;
3511 		uint64_t reserved_62_62:1;
3512 		uint64_t srio3:1;
3513 		uint64_t srio2:1;
3514 		uint64_t reserved_57_59:3;
3515 		uint64_t dfm:1;
3516 		uint64_t reserved_53_55:3;
3517 		uint64_t lmc0:1;
3518 		uint64_t reserved_51_51:1;
3519 		uint64_t srio0:1;
3520 		uint64_t pem1:1;
3521 		uint64_t pem0:1;
3522 		uint64_t ptp:1;
3523 		uint64_t agl:1;
3524 		uint64_t reserved_38_45:8;
3525 		uint64_t agx1:1;
3526 		uint64_t agx0:1;
3527 		uint64_t dpi:1;
3528 		uint64_t sli:1;
3529 		uint64_t usb:1;
3530 		uint64_t dfa:1;
3531 		uint64_t key:1;
3532 		uint64_t rad:1;
3533 		uint64_t tim:1;
3534 		uint64_t zip:1;
3535 		uint64_t pko:1;
3536 		uint64_t pip:1;
3537 		uint64_t ipd:1;
3538 		uint64_t l2c:1;
3539 		uint64_t pow:1;
3540 		uint64_t fpa:1;
3541 		uint64_t iob:1;
3542 		uint64_t mio:1;
3543 		uint64_t nand:1;
3544 		uint64_t mii1:1;
3545 		uint64_t reserved_10_17:8;
3546 		uint64_t wdog:10;
3547 #else
3548 		uint64_t wdog:10;
3549 		uint64_t reserved_10_17:8;
3550 		uint64_t mii1:1;
3551 		uint64_t nand:1;
3552 		uint64_t mio:1;
3553 		uint64_t iob:1;
3554 		uint64_t fpa:1;
3555 		uint64_t pow:1;
3556 		uint64_t l2c:1;
3557 		uint64_t ipd:1;
3558 		uint64_t pip:1;
3559 		uint64_t pko:1;
3560 		uint64_t zip:1;
3561 		uint64_t tim:1;
3562 		uint64_t rad:1;
3563 		uint64_t key:1;
3564 		uint64_t dfa:1;
3565 		uint64_t usb:1;
3566 		uint64_t sli:1;
3567 		uint64_t dpi:1;
3568 		uint64_t agx0:1;
3569 		uint64_t agx1:1;
3570 		uint64_t reserved_38_45:8;
3571 		uint64_t agl:1;
3572 		uint64_t ptp:1;
3573 		uint64_t pem0:1;
3574 		uint64_t pem1:1;
3575 		uint64_t srio0:1;
3576 		uint64_t reserved_51_51:1;
3577 		uint64_t lmc0:1;
3578 		uint64_t reserved_53_55:3;
3579 		uint64_t dfm:1;
3580 		uint64_t reserved_57_59:3;
3581 		uint64_t srio2:1;
3582 		uint64_t srio3:1;
3583 		uint64_t reserved_62_62:1;
3584 		uint64_t rst:1;
3585 #endif
3586 	} cn66xx;
3587 	struct cvmx_ciu_intx_en1_w1s_cnf71xx {
3588 #ifdef __BIG_ENDIAN_BITFIELD
3589 		uint64_t rst:1;
3590 		uint64_t reserved_53_62:10;
3591 		uint64_t lmc0:1;
3592 		uint64_t reserved_50_51:2;
3593 		uint64_t pem1:1;
3594 		uint64_t pem0:1;
3595 		uint64_t ptp:1;
3596 		uint64_t reserved_41_46:6;
3597 		uint64_t dpi_dma:1;
3598 		uint64_t reserved_37_39:3;
3599 		uint64_t agx0:1;
3600 		uint64_t dpi:1;
3601 		uint64_t sli:1;
3602 		uint64_t usb:1;
3603 		uint64_t reserved_32_32:1;
3604 		uint64_t key:1;
3605 		uint64_t rad:1;
3606 		uint64_t tim:1;
3607 		uint64_t reserved_28_28:1;
3608 		uint64_t pko:1;
3609 		uint64_t pip:1;
3610 		uint64_t ipd:1;
3611 		uint64_t l2c:1;
3612 		uint64_t pow:1;
3613 		uint64_t fpa:1;
3614 		uint64_t iob:1;
3615 		uint64_t mio:1;
3616 		uint64_t nand:1;
3617 		uint64_t reserved_4_18:15;
3618 		uint64_t wdog:4;
3619 #else
3620 		uint64_t wdog:4;
3621 		uint64_t reserved_4_18:15;
3622 		uint64_t nand:1;
3623 		uint64_t mio:1;
3624 		uint64_t iob:1;
3625 		uint64_t fpa:1;
3626 		uint64_t pow:1;
3627 		uint64_t l2c:1;
3628 		uint64_t ipd:1;
3629 		uint64_t pip:1;
3630 		uint64_t pko:1;
3631 		uint64_t reserved_28_28:1;
3632 		uint64_t tim:1;
3633 		uint64_t rad:1;
3634 		uint64_t key:1;
3635 		uint64_t reserved_32_32:1;
3636 		uint64_t usb:1;
3637 		uint64_t sli:1;
3638 		uint64_t dpi:1;
3639 		uint64_t agx0:1;
3640 		uint64_t reserved_37_39:3;
3641 		uint64_t dpi_dma:1;
3642 		uint64_t reserved_41_46:6;
3643 		uint64_t ptp:1;
3644 		uint64_t pem0:1;
3645 		uint64_t pem1:1;
3646 		uint64_t reserved_50_51:2;
3647 		uint64_t lmc0:1;
3648 		uint64_t reserved_53_62:10;
3649 		uint64_t rst:1;
3650 #endif
3651 	} cnf71xx;
3652 };
3653 
3654 union cvmx_ciu_intx_en4_0 {
3655 	uint64_t u64;
3656 	struct cvmx_ciu_intx_en4_0_s {
3657 #ifdef __BIG_ENDIAN_BITFIELD
3658 		uint64_t bootdma:1;
3659 		uint64_t mii:1;
3660 		uint64_t ipdppthr:1;
3661 		uint64_t powiq:1;
3662 		uint64_t twsi2:1;
3663 		uint64_t mpi:1;
3664 		uint64_t pcm:1;
3665 		uint64_t usb:1;
3666 		uint64_t timer:4;
3667 		uint64_t key_zero:1;
3668 		uint64_t ipd_drp:1;
3669 		uint64_t gmx_drp:2;
3670 		uint64_t trace:1;
3671 		uint64_t rml:1;
3672 		uint64_t twsi:1;
3673 		uint64_t reserved_44_44:1;
3674 		uint64_t pci_msi:4;
3675 		uint64_t pci_int:4;
3676 		uint64_t uart:2;
3677 		uint64_t mbox:2;
3678 		uint64_t gpio:16;
3679 		uint64_t workq:16;
3680 #else
3681 		uint64_t workq:16;
3682 		uint64_t gpio:16;
3683 		uint64_t mbox:2;
3684 		uint64_t uart:2;
3685 		uint64_t pci_int:4;
3686 		uint64_t pci_msi:4;
3687 		uint64_t reserved_44_44:1;
3688 		uint64_t twsi:1;
3689 		uint64_t rml:1;
3690 		uint64_t trace:1;
3691 		uint64_t gmx_drp:2;
3692 		uint64_t ipd_drp:1;
3693 		uint64_t key_zero:1;
3694 		uint64_t timer:4;
3695 		uint64_t usb:1;
3696 		uint64_t pcm:1;
3697 		uint64_t mpi:1;
3698 		uint64_t twsi2:1;
3699 		uint64_t powiq:1;
3700 		uint64_t ipdppthr:1;
3701 		uint64_t mii:1;
3702 		uint64_t bootdma:1;
3703 #endif
3704 	} s;
3705 	struct cvmx_ciu_intx_en4_0_cn50xx {
3706 #ifdef __BIG_ENDIAN_BITFIELD
3707 		uint64_t reserved_59_63:5;
3708 		uint64_t mpi:1;
3709 		uint64_t pcm:1;
3710 		uint64_t usb:1;
3711 		uint64_t timer:4;
3712 		uint64_t reserved_51_51:1;
3713 		uint64_t ipd_drp:1;
3714 		uint64_t reserved_49_49:1;
3715 		uint64_t gmx_drp:1;
3716 		uint64_t reserved_47_47:1;
3717 		uint64_t rml:1;
3718 		uint64_t twsi:1;
3719 		uint64_t reserved_44_44:1;
3720 		uint64_t pci_msi:4;
3721 		uint64_t pci_int:4;
3722 		uint64_t uart:2;
3723 		uint64_t mbox:2;
3724 		uint64_t gpio:16;
3725 		uint64_t workq:16;
3726 #else
3727 		uint64_t workq:16;
3728 		uint64_t gpio:16;
3729 		uint64_t mbox:2;
3730 		uint64_t uart:2;
3731 		uint64_t pci_int:4;
3732 		uint64_t pci_msi:4;
3733 		uint64_t reserved_44_44:1;
3734 		uint64_t twsi:1;
3735 		uint64_t rml:1;
3736 		uint64_t reserved_47_47:1;
3737 		uint64_t gmx_drp:1;
3738 		uint64_t reserved_49_49:1;
3739 		uint64_t ipd_drp:1;
3740 		uint64_t reserved_51_51:1;
3741 		uint64_t timer:4;
3742 		uint64_t usb:1;
3743 		uint64_t pcm:1;
3744 		uint64_t mpi:1;
3745 		uint64_t reserved_59_63:5;
3746 #endif
3747 	} cn50xx;
3748 	struct cvmx_ciu_intx_en4_0_cn52xx {
3749 #ifdef __BIG_ENDIAN_BITFIELD
3750 		uint64_t bootdma:1;
3751 		uint64_t mii:1;
3752 		uint64_t ipdppthr:1;
3753 		uint64_t powiq:1;
3754 		uint64_t twsi2:1;
3755 		uint64_t reserved_57_58:2;
3756 		uint64_t usb:1;
3757 		uint64_t timer:4;
3758 		uint64_t reserved_51_51:1;
3759 		uint64_t ipd_drp:1;
3760 		uint64_t reserved_49_49:1;
3761 		uint64_t gmx_drp:1;
3762 		uint64_t trace:1;
3763 		uint64_t rml:1;
3764 		uint64_t twsi:1;
3765 		uint64_t reserved_44_44:1;
3766 		uint64_t pci_msi:4;
3767 		uint64_t pci_int:4;
3768 		uint64_t uart:2;
3769 		uint64_t mbox:2;
3770 		uint64_t gpio:16;
3771 		uint64_t workq:16;
3772 #else
3773 		uint64_t workq:16;
3774 		uint64_t gpio:16;
3775 		uint64_t mbox:2;
3776 		uint64_t uart:2;
3777 		uint64_t pci_int:4;
3778 		uint64_t pci_msi:4;
3779 		uint64_t reserved_44_44:1;
3780 		uint64_t twsi:1;
3781 		uint64_t rml:1;
3782 		uint64_t trace:1;
3783 		uint64_t gmx_drp:1;
3784 		uint64_t reserved_49_49:1;
3785 		uint64_t ipd_drp:1;
3786 		uint64_t reserved_51_51:1;
3787 		uint64_t timer:4;
3788 		uint64_t usb:1;
3789 		uint64_t reserved_57_58:2;
3790 		uint64_t twsi2:1;
3791 		uint64_t powiq:1;
3792 		uint64_t ipdppthr:1;
3793 		uint64_t mii:1;
3794 		uint64_t bootdma:1;
3795 #endif
3796 	} cn52xx;
3797 	struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
3798 	struct cvmx_ciu_intx_en4_0_cn56xx {
3799 #ifdef __BIG_ENDIAN_BITFIELD
3800 		uint64_t bootdma:1;
3801 		uint64_t mii:1;
3802 		uint64_t ipdppthr:1;
3803 		uint64_t powiq:1;
3804 		uint64_t twsi2:1;
3805 		uint64_t reserved_57_58:2;
3806 		uint64_t usb:1;
3807 		uint64_t timer:4;
3808 		uint64_t key_zero:1;
3809 		uint64_t ipd_drp:1;
3810 		uint64_t gmx_drp:2;
3811 		uint64_t trace:1;
3812 		uint64_t rml:1;
3813 		uint64_t twsi:1;
3814 		uint64_t reserved_44_44:1;
3815 		uint64_t pci_msi:4;
3816 		uint64_t pci_int:4;
3817 		uint64_t uart:2;
3818 		uint64_t mbox:2;
3819 		uint64_t gpio:16;
3820 		uint64_t workq:16;
3821 #else
3822 		uint64_t workq:16;
3823 		uint64_t gpio:16;
3824 		uint64_t mbox:2;
3825 		uint64_t uart:2;
3826 		uint64_t pci_int:4;
3827 		uint64_t pci_msi:4;
3828 		uint64_t reserved_44_44:1;
3829 		uint64_t twsi:1;
3830 		uint64_t rml:1;
3831 		uint64_t trace:1;
3832 		uint64_t gmx_drp:2;
3833 		uint64_t ipd_drp:1;
3834 		uint64_t key_zero:1;
3835 		uint64_t timer:4;
3836 		uint64_t usb:1;
3837 		uint64_t reserved_57_58:2;
3838 		uint64_t twsi2:1;
3839 		uint64_t powiq:1;
3840 		uint64_t ipdppthr:1;
3841 		uint64_t mii:1;
3842 		uint64_t bootdma:1;
3843 #endif
3844 	} cn56xx;
3845 	struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
3846 	struct cvmx_ciu_intx_en4_0_cn58xx {
3847 #ifdef __BIG_ENDIAN_BITFIELD
3848 		uint64_t reserved_56_63:8;
3849 		uint64_t timer:4;
3850 		uint64_t key_zero:1;
3851 		uint64_t ipd_drp:1;
3852 		uint64_t gmx_drp:2;
3853 		uint64_t trace:1;
3854 		uint64_t rml:1;
3855 		uint64_t twsi:1;
3856 		uint64_t reserved_44_44:1;
3857 		uint64_t pci_msi:4;
3858 		uint64_t pci_int:4;
3859 		uint64_t uart:2;
3860 		uint64_t mbox:2;
3861 		uint64_t gpio:16;
3862 		uint64_t workq:16;
3863 #else
3864 		uint64_t workq:16;
3865 		uint64_t gpio:16;
3866 		uint64_t mbox:2;
3867 		uint64_t uart:2;
3868 		uint64_t pci_int:4;
3869 		uint64_t pci_msi:4;
3870 		uint64_t reserved_44_44:1;
3871 		uint64_t twsi:1;
3872 		uint64_t rml:1;
3873 		uint64_t trace:1;
3874 		uint64_t gmx_drp:2;
3875 		uint64_t ipd_drp:1;
3876 		uint64_t key_zero:1;
3877 		uint64_t timer:4;
3878 		uint64_t reserved_56_63:8;
3879 #endif
3880 	} cn58xx;
3881 	struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
3882 	struct cvmx_ciu_intx_en4_0_cn61xx {
3883 #ifdef __BIG_ENDIAN_BITFIELD
3884 		uint64_t bootdma:1;
3885 		uint64_t mii:1;
3886 		uint64_t ipdppthr:1;
3887 		uint64_t powiq:1;
3888 		uint64_t twsi2:1;
3889 		uint64_t mpi:1;
3890 		uint64_t pcm:1;
3891 		uint64_t usb:1;
3892 		uint64_t timer:4;
3893 		uint64_t reserved_51_51:1;
3894 		uint64_t ipd_drp:1;
3895 		uint64_t gmx_drp:2;
3896 		uint64_t trace:1;
3897 		uint64_t rml:1;
3898 		uint64_t twsi:1;
3899 		uint64_t reserved_44_44:1;
3900 		uint64_t pci_msi:4;
3901 		uint64_t pci_int:4;
3902 		uint64_t uart:2;
3903 		uint64_t mbox:2;
3904 		uint64_t gpio:16;
3905 		uint64_t workq:16;
3906 #else
3907 		uint64_t workq:16;
3908 		uint64_t gpio:16;
3909 		uint64_t mbox:2;
3910 		uint64_t uart:2;
3911 		uint64_t pci_int:4;
3912 		uint64_t pci_msi:4;
3913 		uint64_t reserved_44_44:1;
3914 		uint64_t twsi:1;
3915 		uint64_t rml:1;
3916 		uint64_t trace:1;
3917 		uint64_t gmx_drp:2;
3918 		uint64_t ipd_drp:1;
3919 		uint64_t reserved_51_51:1;
3920 		uint64_t timer:4;
3921 		uint64_t usb:1;
3922 		uint64_t pcm:1;
3923 		uint64_t mpi:1;
3924 		uint64_t twsi2:1;
3925 		uint64_t powiq:1;
3926 		uint64_t ipdppthr:1;
3927 		uint64_t mii:1;
3928 		uint64_t bootdma:1;
3929 #endif
3930 	} cn61xx;
3931 	struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
3932 	struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
3933 	struct cvmx_ciu_intx_en4_0_cn66xx {
3934 #ifdef __BIG_ENDIAN_BITFIELD
3935 		uint64_t bootdma:1;
3936 		uint64_t mii:1;
3937 		uint64_t ipdppthr:1;
3938 		uint64_t powiq:1;
3939 		uint64_t twsi2:1;
3940 		uint64_t mpi:1;
3941 		uint64_t reserved_57_57:1;
3942 		uint64_t usb:1;
3943 		uint64_t timer:4;
3944 		uint64_t reserved_51_51:1;
3945 		uint64_t ipd_drp:1;
3946 		uint64_t gmx_drp:2;
3947 		uint64_t trace:1;
3948 		uint64_t rml:1;
3949 		uint64_t twsi:1;
3950 		uint64_t reserved_44_44:1;
3951 		uint64_t pci_msi:4;
3952 		uint64_t pci_int:4;
3953 		uint64_t uart:2;
3954 		uint64_t mbox:2;
3955 		uint64_t gpio:16;
3956 		uint64_t workq:16;
3957 #else
3958 		uint64_t workq:16;
3959 		uint64_t gpio:16;
3960 		uint64_t mbox:2;
3961 		uint64_t uart:2;
3962 		uint64_t pci_int:4;
3963 		uint64_t pci_msi:4;
3964 		uint64_t reserved_44_44:1;
3965 		uint64_t twsi:1;
3966 		uint64_t rml:1;
3967 		uint64_t trace:1;
3968 		uint64_t gmx_drp:2;
3969 		uint64_t ipd_drp:1;
3970 		uint64_t reserved_51_51:1;
3971 		uint64_t timer:4;
3972 		uint64_t usb:1;
3973 		uint64_t reserved_57_57:1;
3974 		uint64_t mpi:1;
3975 		uint64_t twsi2:1;
3976 		uint64_t powiq:1;
3977 		uint64_t ipdppthr:1;
3978 		uint64_t mii:1;
3979 		uint64_t bootdma:1;
3980 #endif
3981 	} cn66xx;
3982 	struct cvmx_ciu_intx_en4_0_cnf71xx {
3983 #ifdef __BIG_ENDIAN_BITFIELD
3984 		uint64_t bootdma:1;
3985 		uint64_t reserved_62_62:1;
3986 		uint64_t ipdppthr:1;
3987 		uint64_t powiq:1;
3988 		uint64_t twsi2:1;
3989 		uint64_t mpi:1;
3990 		uint64_t pcm:1;
3991 		uint64_t usb:1;
3992 		uint64_t timer:4;
3993 		uint64_t reserved_51_51:1;
3994 		uint64_t ipd_drp:1;
3995 		uint64_t reserved_49_49:1;
3996 		uint64_t gmx_drp:1;
3997 		uint64_t trace:1;
3998 		uint64_t rml:1;
3999 		uint64_t twsi:1;
4000 		uint64_t reserved_44_44:1;
4001 		uint64_t pci_msi:4;
4002 		uint64_t pci_int:4;
4003 		uint64_t uart:2;
4004 		uint64_t mbox:2;
4005 		uint64_t gpio:16;
4006 		uint64_t workq:16;
4007 #else
4008 		uint64_t workq:16;
4009 		uint64_t gpio:16;
4010 		uint64_t mbox:2;
4011 		uint64_t uart:2;
4012 		uint64_t pci_int:4;
4013 		uint64_t pci_msi:4;
4014 		uint64_t reserved_44_44:1;
4015 		uint64_t twsi:1;
4016 		uint64_t rml:1;
4017 		uint64_t trace:1;
4018 		uint64_t gmx_drp:1;
4019 		uint64_t reserved_49_49:1;
4020 		uint64_t ipd_drp:1;
4021 		uint64_t reserved_51_51:1;
4022 		uint64_t timer:4;
4023 		uint64_t usb:1;
4024 		uint64_t pcm:1;
4025 		uint64_t mpi:1;
4026 		uint64_t twsi2:1;
4027 		uint64_t powiq:1;
4028 		uint64_t ipdppthr:1;
4029 		uint64_t reserved_62_62:1;
4030 		uint64_t bootdma:1;
4031 #endif
4032 	} cnf71xx;
4033 };
4034 
4035 union cvmx_ciu_intx_en4_0_w1c {
4036 	uint64_t u64;
4037 	struct cvmx_ciu_intx_en4_0_w1c_s {
4038 #ifdef __BIG_ENDIAN_BITFIELD
4039 		uint64_t bootdma:1;
4040 		uint64_t mii:1;
4041 		uint64_t ipdppthr:1;
4042 		uint64_t powiq:1;
4043 		uint64_t twsi2:1;
4044 		uint64_t mpi:1;
4045 		uint64_t pcm:1;
4046 		uint64_t usb:1;
4047 		uint64_t timer:4;
4048 		uint64_t key_zero:1;
4049 		uint64_t ipd_drp:1;
4050 		uint64_t gmx_drp:2;
4051 		uint64_t trace:1;
4052 		uint64_t rml:1;
4053 		uint64_t twsi:1;
4054 		uint64_t reserved_44_44:1;
4055 		uint64_t pci_msi:4;
4056 		uint64_t pci_int:4;
4057 		uint64_t uart:2;
4058 		uint64_t mbox:2;
4059 		uint64_t gpio:16;
4060 		uint64_t workq:16;
4061 #else
4062 		uint64_t workq:16;
4063 		uint64_t gpio:16;
4064 		uint64_t mbox:2;
4065 		uint64_t uart:2;
4066 		uint64_t pci_int:4;
4067 		uint64_t pci_msi:4;
4068 		uint64_t reserved_44_44:1;
4069 		uint64_t twsi:1;
4070 		uint64_t rml:1;
4071 		uint64_t trace:1;
4072 		uint64_t gmx_drp:2;
4073 		uint64_t ipd_drp:1;
4074 		uint64_t key_zero:1;
4075 		uint64_t timer:4;
4076 		uint64_t usb:1;
4077 		uint64_t pcm:1;
4078 		uint64_t mpi:1;
4079 		uint64_t twsi2:1;
4080 		uint64_t powiq:1;
4081 		uint64_t ipdppthr:1;
4082 		uint64_t mii:1;
4083 		uint64_t bootdma:1;
4084 #endif
4085 	} s;
4086 	struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
4087 #ifdef __BIG_ENDIAN_BITFIELD
4088 		uint64_t bootdma:1;
4089 		uint64_t mii:1;
4090 		uint64_t ipdppthr:1;
4091 		uint64_t powiq:1;
4092 		uint64_t twsi2:1;
4093 		uint64_t reserved_57_58:2;
4094 		uint64_t usb:1;
4095 		uint64_t timer:4;
4096 		uint64_t reserved_51_51:1;
4097 		uint64_t ipd_drp:1;
4098 		uint64_t reserved_49_49:1;
4099 		uint64_t gmx_drp:1;
4100 		uint64_t trace:1;
4101 		uint64_t rml:1;
4102 		uint64_t twsi:1;
4103 		uint64_t reserved_44_44:1;
4104 		uint64_t pci_msi:4;
4105 		uint64_t pci_int:4;
4106 		uint64_t uart:2;
4107 		uint64_t mbox:2;
4108 		uint64_t gpio:16;
4109 		uint64_t workq:16;
4110 #else
4111 		uint64_t workq:16;
4112 		uint64_t gpio:16;
4113 		uint64_t mbox:2;
4114 		uint64_t uart:2;
4115 		uint64_t pci_int:4;
4116 		uint64_t pci_msi:4;
4117 		uint64_t reserved_44_44:1;
4118 		uint64_t twsi:1;
4119 		uint64_t rml:1;
4120 		uint64_t trace:1;
4121 		uint64_t gmx_drp:1;
4122 		uint64_t reserved_49_49:1;
4123 		uint64_t ipd_drp:1;
4124 		uint64_t reserved_51_51:1;
4125 		uint64_t timer:4;
4126 		uint64_t usb:1;
4127 		uint64_t reserved_57_58:2;
4128 		uint64_t twsi2:1;
4129 		uint64_t powiq:1;
4130 		uint64_t ipdppthr:1;
4131 		uint64_t mii:1;
4132 		uint64_t bootdma:1;
4133 #endif
4134 	} cn52xx;
4135 	struct cvmx_ciu_intx_en4_0_w1c_cn56xx {
4136 #ifdef __BIG_ENDIAN_BITFIELD
4137 		uint64_t bootdma:1;
4138 		uint64_t mii:1;
4139 		uint64_t ipdppthr:1;
4140 		uint64_t powiq:1;
4141 		uint64_t twsi2:1;
4142 		uint64_t reserved_57_58:2;
4143 		uint64_t usb:1;
4144 		uint64_t timer:4;
4145 		uint64_t key_zero:1;
4146 		uint64_t ipd_drp:1;
4147 		uint64_t gmx_drp:2;
4148 		uint64_t trace:1;
4149 		uint64_t rml:1;
4150 		uint64_t twsi:1;
4151 		uint64_t reserved_44_44:1;
4152 		uint64_t pci_msi:4;
4153 		uint64_t pci_int:4;
4154 		uint64_t uart:2;
4155 		uint64_t mbox:2;
4156 		uint64_t gpio:16;
4157 		uint64_t workq:16;
4158 #else
4159 		uint64_t workq:16;
4160 		uint64_t gpio:16;
4161 		uint64_t mbox:2;
4162 		uint64_t uart:2;
4163 		uint64_t pci_int:4;
4164 		uint64_t pci_msi:4;
4165 		uint64_t reserved_44_44:1;
4166 		uint64_t twsi:1;
4167 		uint64_t rml:1;
4168 		uint64_t trace:1;
4169 		uint64_t gmx_drp:2;
4170 		uint64_t ipd_drp:1;
4171 		uint64_t key_zero:1;
4172 		uint64_t timer:4;
4173 		uint64_t usb:1;
4174 		uint64_t reserved_57_58:2;
4175 		uint64_t twsi2:1;
4176 		uint64_t powiq:1;
4177 		uint64_t ipdppthr:1;
4178 		uint64_t mii:1;
4179 		uint64_t bootdma:1;
4180 #endif
4181 	} cn56xx;
4182 	struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
4183 #ifdef __BIG_ENDIAN_BITFIELD
4184 		uint64_t reserved_56_63:8;
4185 		uint64_t timer:4;
4186 		uint64_t key_zero:1;
4187 		uint64_t ipd_drp:1;
4188 		uint64_t gmx_drp:2;
4189 		uint64_t trace:1;
4190 		uint64_t rml:1;
4191 		uint64_t twsi:1;
4192 		uint64_t reserved_44_44:1;
4193 		uint64_t pci_msi:4;
4194 		uint64_t pci_int:4;
4195 		uint64_t uart:2;
4196 		uint64_t mbox:2;
4197 		uint64_t gpio:16;
4198 		uint64_t workq:16;
4199 #else
4200 		uint64_t workq:16;
4201 		uint64_t gpio:16;
4202 		uint64_t mbox:2;
4203 		uint64_t uart:2;
4204 		uint64_t pci_int:4;
4205 		uint64_t pci_msi:4;
4206 		uint64_t reserved_44_44:1;
4207 		uint64_t twsi:1;
4208 		uint64_t rml:1;
4209 		uint64_t trace:1;
4210 		uint64_t gmx_drp:2;
4211 		uint64_t ipd_drp:1;
4212 		uint64_t key_zero:1;
4213 		uint64_t timer:4;
4214 		uint64_t reserved_56_63:8;
4215 #endif
4216 	} cn58xx;
4217 	struct cvmx_ciu_intx_en4_0_w1c_cn61xx {
4218 #ifdef __BIG_ENDIAN_BITFIELD
4219 		uint64_t bootdma:1;
4220 		uint64_t mii:1;
4221 		uint64_t ipdppthr:1;
4222 		uint64_t powiq:1;
4223 		uint64_t twsi2:1;
4224 		uint64_t mpi:1;
4225 		uint64_t pcm:1;
4226 		uint64_t usb:1;
4227 		uint64_t timer:4;
4228 		uint64_t reserved_51_51:1;
4229 		uint64_t ipd_drp:1;
4230 		uint64_t gmx_drp:2;
4231 		uint64_t trace:1;
4232 		uint64_t rml:1;
4233 		uint64_t twsi:1;
4234 		uint64_t reserved_44_44:1;
4235 		uint64_t pci_msi:4;
4236 		uint64_t pci_int:4;
4237 		uint64_t uart:2;
4238 		uint64_t mbox:2;
4239 		uint64_t gpio:16;
4240 		uint64_t workq:16;
4241 #else
4242 		uint64_t workq:16;
4243 		uint64_t gpio:16;
4244 		uint64_t mbox:2;
4245 		uint64_t uart:2;
4246 		uint64_t pci_int:4;
4247 		uint64_t pci_msi:4;
4248 		uint64_t reserved_44_44:1;
4249 		uint64_t twsi:1;
4250 		uint64_t rml:1;
4251 		uint64_t trace:1;
4252 		uint64_t gmx_drp:2;
4253 		uint64_t ipd_drp:1;
4254 		uint64_t reserved_51_51:1;
4255 		uint64_t timer:4;
4256 		uint64_t usb:1;
4257 		uint64_t pcm:1;
4258 		uint64_t mpi:1;
4259 		uint64_t twsi2:1;
4260 		uint64_t powiq:1;
4261 		uint64_t ipdppthr:1;
4262 		uint64_t mii:1;
4263 		uint64_t bootdma:1;
4264 #endif
4265 	} cn61xx;
4266 	struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
4267 	struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
4268 	struct cvmx_ciu_intx_en4_0_w1c_cn66xx {
4269 #ifdef __BIG_ENDIAN_BITFIELD
4270 		uint64_t bootdma:1;
4271 		uint64_t mii:1;
4272 		uint64_t ipdppthr:1;
4273 		uint64_t powiq:1;
4274 		uint64_t twsi2:1;
4275 		uint64_t mpi:1;
4276 		uint64_t reserved_57_57:1;
4277 		uint64_t usb:1;
4278 		uint64_t timer:4;
4279 		uint64_t reserved_51_51:1;
4280 		uint64_t ipd_drp:1;
4281 		uint64_t gmx_drp:2;
4282 		uint64_t trace:1;
4283 		uint64_t rml:1;
4284 		uint64_t twsi:1;
4285 		uint64_t reserved_44_44:1;
4286 		uint64_t pci_msi:4;
4287 		uint64_t pci_int:4;
4288 		uint64_t uart:2;
4289 		uint64_t mbox:2;
4290 		uint64_t gpio:16;
4291 		uint64_t workq:16;
4292 #else
4293 		uint64_t workq:16;
4294 		uint64_t gpio:16;
4295 		uint64_t mbox:2;
4296 		uint64_t uart:2;
4297 		uint64_t pci_int:4;
4298 		uint64_t pci_msi:4;
4299 		uint64_t reserved_44_44:1;
4300 		uint64_t twsi:1;
4301 		uint64_t rml:1;
4302 		uint64_t trace:1;
4303 		uint64_t gmx_drp:2;
4304 		uint64_t ipd_drp:1;
4305 		uint64_t reserved_51_51:1;
4306 		uint64_t timer:4;
4307 		uint64_t usb:1;
4308 		uint64_t reserved_57_57:1;
4309 		uint64_t mpi:1;
4310 		uint64_t twsi2:1;
4311 		uint64_t powiq:1;
4312 		uint64_t ipdppthr:1;
4313 		uint64_t mii:1;
4314 		uint64_t bootdma:1;
4315 #endif
4316 	} cn66xx;
4317 	struct cvmx_ciu_intx_en4_0_w1c_cnf71xx {
4318 #ifdef __BIG_ENDIAN_BITFIELD
4319 		uint64_t bootdma:1;
4320 		uint64_t reserved_62_62:1;
4321 		uint64_t ipdppthr:1;
4322 		uint64_t powiq:1;
4323 		uint64_t twsi2:1;
4324 		uint64_t mpi:1;
4325 		uint64_t pcm:1;
4326 		uint64_t usb:1;
4327 		uint64_t timer:4;
4328 		uint64_t reserved_51_51:1;
4329 		uint64_t ipd_drp:1;
4330 		uint64_t reserved_49_49:1;
4331 		uint64_t gmx_drp:1;
4332 		uint64_t trace:1;
4333 		uint64_t rml:1;
4334 		uint64_t twsi:1;
4335 		uint64_t reserved_44_44:1;
4336 		uint64_t pci_msi:4;
4337 		uint64_t pci_int:4;
4338 		uint64_t uart:2;
4339 		uint64_t mbox:2;
4340 		uint64_t gpio:16;
4341 		uint64_t workq:16;
4342 #else
4343 		uint64_t workq:16;
4344 		uint64_t gpio:16;
4345 		uint64_t mbox:2;
4346 		uint64_t uart:2;
4347 		uint64_t pci_int:4;
4348 		uint64_t pci_msi:4;
4349 		uint64_t reserved_44_44:1;
4350 		uint64_t twsi:1;
4351 		uint64_t rml:1;
4352 		uint64_t trace:1;
4353 		uint64_t gmx_drp:1;
4354 		uint64_t reserved_49_49:1;
4355 		uint64_t ipd_drp:1;
4356 		uint64_t reserved_51_51:1;
4357 		uint64_t timer:4;
4358 		uint64_t usb:1;
4359 		uint64_t pcm:1;
4360 		uint64_t mpi:1;
4361 		uint64_t twsi2:1;
4362 		uint64_t powiq:1;
4363 		uint64_t ipdppthr:1;
4364 		uint64_t reserved_62_62:1;
4365 		uint64_t bootdma:1;
4366 #endif
4367 	} cnf71xx;
4368 };
4369 
4370 union cvmx_ciu_intx_en4_0_w1s {
4371 	uint64_t u64;
4372 	struct cvmx_ciu_intx_en4_0_w1s_s {
4373 #ifdef __BIG_ENDIAN_BITFIELD
4374 		uint64_t bootdma:1;
4375 		uint64_t mii:1;
4376 		uint64_t ipdppthr:1;
4377 		uint64_t powiq:1;
4378 		uint64_t twsi2:1;
4379 		uint64_t mpi:1;
4380 		uint64_t pcm:1;
4381 		uint64_t usb:1;
4382 		uint64_t timer:4;
4383 		uint64_t key_zero:1;
4384 		uint64_t ipd_drp:1;
4385 		uint64_t gmx_drp:2;
4386 		uint64_t trace:1;
4387 		uint64_t rml:1;
4388 		uint64_t twsi:1;
4389 		uint64_t reserved_44_44:1;
4390 		uint64_t pci_msi:4;
4391 		uint64_t pci_int:4;
4392 		uint64_t uart:2;
4393 		uint64_t mbox:2;
4394 		uint64_t gpio:16;
4395 		uint64_t workq:16;
4396 #else
4397 		uint64_t workq:16;
4398 		uint64_t gpio:16;
4399 		uint64_t mbox:2;
4400 		uint64_t uart:2;
4401 		uint64_t pci_int:4;
4402 		uint64_t pci_msi:4;
4403 		uint64_t reserved_44_44:1;
4404 		uint64_t twsi:1;
4405 		uint64_t rml:1;
4406 		uint64_t trace:1;
4407 		uint64_t gmx_drp:2;
4408 		uint64_t ipd_drp:1;
4409 		uint64_t key_zero:1;
4410 		uint64_t timer:4;
4411 		uint64_t usb:1;
4412 		uint64_t pcm:1;
4413 		uint64_t mpi:1;
4414 		uint64_t twsi2:1;
4415 		uint64_t powiq:1;
4416 		uint64_t ipdppthr:1;
4417 		uint64_t mii:1;
4418 		uint64_t bootdma:1;
4419 #endif
4420 	} s;
4421 	struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
4422 #ifdef __BIG_ENDIAN_BITFIELD
4423 		uint64_t bootdma:1;
4424 		uint64_t mii:1;
4425 		uint64_t ipdppthr:1;
4426 		uint64_t powiq:1;
4427 		uint64_t twsi2:1;
4428 		uint64_t reserved_57_58:2;
4429 		uint64_t usb:1;
4430 		uint64_t timer:4;
4431 		uint64_t reserved_51_51:1;
4432 		uint64_t ipd_drp:1;
4433 		uint64_t reserved_49_49:1;
4434 		uint64_t gmx_drp:1;
4435 		uint64_t trace:1;
4436 		uint64_t rml:1;
4437 		uint64_t twsi:1;
4438 		uint64_t reserved_44_44:1;
4439 		uint64_t pci_msi:4;
4440 		uint64_t pci_int:4;
4441 		uint64_t uart:2;
4442 		uint64_t mbox:2;
4443 		uint64_t gpio:16;
4444 		uint64_t workq:16;
4445 #else
4446 		uint64_t workq:16;
4447 		uint64_t gpio:16;
4448 		uint64_t mbox:2;
4449 		uint64_t uart:2;
4450 		uint64_t pci_int:4;
4451 		uint64_t pci_msi:4;
4452 		uint64_t reserved_44_44:1;
4453 		uint64_t twsi:1;
4454 		uint64_t rml:1;
4455 		uint64_t trace:1;
4456 		uint64_t gmx_drp:1;
4457 		uint64_t reserved_49_49:1;
4458 		uint64_t ipd_drp:1;
4459 		uint64_t reserved_51_51:1;
4460 		uint64_t timer:4;
4461 		uint64_t usb:1;
4462 		uint64_t reserved_57_58:2;
4463 		uint64_t twsi2:1;
4464 		uint64_t powiq:1;
4465 		uint64_t ipdppthr:1;
4466 		uint64_t mii:1;
4467 		uint64_t bootdma:1;
4468 #endif
4469 	} cn52xx;
4470 	struct cvmx_ciu_intx_en4_0_w1s_cn56xx {
4471 #ifdef __BIG_ENDIAN_BITFIELD
4472 		uint64_t bootdma:1;
4473 		uint64_t mii:1;
4474 		uint64_t ipdppthr:1;
4475 		uint64_t powiq:1;
4476 		uint64_t twsi2:1;
4477 		uint64_t reserved_57_58:2;
4478 		uint64_t usb:1;
4479 		uint64_t timer:4;
4480 		uint64_t key_zero:1;
4481 		uint64_t ipd_drp:1;
4482 		uint64_t gmx_drp:2;
4483 		uint64_t trace:1;
4484 		uint64_t rml:1;
4485 		uint64_t twsi:1;
4486 		uint64_t reserved_44_44:1;
4487 		uint64_t pci_msi:4;
4488 		uint64_t pci_int:4;
4489 		uint64_t uart:2;
4490 		uint64_t mbox:2;
4491 		uint64_t gpio:16;
4492 		uint64_t workq:16;
4493 #else
4494 		uint64_t workq:16;
4495 		uint64_t gpio:16;
4496 		uint64_t mbox:2;
4497 		uint64_t uart:2;
4498 		uint64_t pci_int:4;
4499 		uint64_t pci_msi:4;
4500 		uint64_t reserved_44_44:1;
4501 		uint64_t twsi:1;
4502 		uint64_t rml:1;
4503 		uint64_t trace:1;
4504 		uint64_t gmx_drp:2;
4505 		uint64_t ipd_drp:1;
4506 		uint64_t key_zero:1;
4507 		uint64_t timer:4;
4508 		uint64_t usb:1;
4509 		uint64_t reserved_57_58:2;
4510 		uint64_t twsi2:1;
4511 		uint64_t powiq:1;
4512 		uint64_t ipdppthr:1;
4513 		uint64_t mii:1;
4514 		uint64_t bootdma:1;
4515 #endif
4516 	} cn56xx;
4517 	struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
4518 #ifdef __BIG_ENDIAN_BITFIELD
4519 		uint64_t reserved_56_63:8;
4520 		uint64_t timer:4;
4521 		uint64_t key_zero:1;
4522 		uint64_t ipd_drp:1;
4523 		uint64_t gmx_drp:2;
4524 		uint64_t trace:1;
4525 		uint64_t rml:1;
4526 		uint64_t twsi:1;
4527 		uint64_t reserved_44_44:1;
4528 		uint64_t pci_msi:4;
4529 		uint64_t pci_int:4;
4530 		uint64_t uart:2;
4531 		uint64_t mbox:2;
4532 		uint64_t gpio:16;
4533 		uint64_t workq:16;
4534 #else
4535 		uint64_t workq:16;
4536 		uint64_t gpio:16;
4537 		uint64_t mbox:2;
4538 		uint64_t uart:2;
4539 		uint64_t pci_int:4;
4540 		uint64_t pci_msi:4;
4541 		uint64_t reserved_44_44:1;
4542 		uint64_t twsi:1;
4543 		uint64_t rml:1;
4544 		uint64_t trace:1;
4545 		uint64_t gmx_drp:2;
4546 		uint64_t ipd_drp:1;
4547 		uint64_t key_zero:1;
4548 		uint64_t timer:4;
4549 		uint64_t reserved_56_63:8;
4550 #endif
4551 	} cn58xx;
4552 	struct cvmx_ciu_intx_en4_0_w1s_cn61xx {
4553 #ifdef __BIG_ENDIAN_BITFIELD
4554 		uint64_t bootdma:1;
4555 		uint64_t mii:1;
4556 		uint64_t ipdppthr:1;
4557 		uint64_t powiq:1;
4558 		uint64_t twsi2:1;
4559 		uint64_t mpi:1;
4560 		uint64_t pcm:1;
4561 		uint64_t usb:1;
4562 		uint64_t timer:4;
4563 		uint64_t reserved_51_51:1;
4564 		uint64_t ipd_drp:1;
4565 		uint64_t gmx_drp:2;
4566 		uint64_t trace:1;
4567 		uint64_t rml:1;
4568 		uint64_t twsi:1;
4569 		uint64_t reserved_44_44:1;
4570 		uint64_t pci_msi:4;
4571 		uint64_t pci_int:4;
4572 		uint64_t uart:2;
4573 		uint64_t mbox:2;
4574 		uint64_t gpio:16;
4575 		uint64_t workq:16;
4576 #else
4577 		uint64_t workq:16;
4578 		uint64_t gpio:16;
4579 		uint64_t mbox:2;
4580 		uint64_t uart:2;
4581 		uint64_t pci_int:4;
4582 		uint64_t pci_msi:4;
4583 		uint64_t reserved_44_44:1;
4584 		uint64_t twsi:1;
4585 		uint64_t rml:1;
4586 		uint64_t trace:1;
4587 		uint64_t gmx_drp:2;
4588 		uint64_t ipd_drp:1;
4589 		uint64_t reserved_51_51:1;
4590 		uint64_t timer:4;
4591 		uint64_t usb:1;
4592 		uint64_t pcm:1;
4593 		uint64_t mpi:1;
4594 		uint64_t twsi2:1;
4595 		uint64_t powiq:1;
4596 		uint64_t ipdppthr:1;
4597 		uint64_t mii:1;
4598 		uint64_t bootdma:1;
4599 #endif
4600 	} cn61xx;
4601 	struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
4602 	struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
4603 	struct cvmx_ciu_intx_en4_0_w1s_cn66xx {
4604 #ifdef __BIG_ENDIAN_BITFIELD
4605 		uint64_t bootdma:1;
4606 		uint64_t mii:1;
4607 		uint64_t ipdppthr:1;
4608 		uint64_t powiq:1;
4609 		uint64_t twsi2:1;
4610 		uint64_t mpi:1;
4611 		uint64_t reserved_57_57:1;
4612 		uint64_t usb:1;
4613 		uint64_t timer:4;
4614 		uint64_t reserved_51_51:1;
4615 		uint64_t ipd_drp:1;
4616 		uint64_t gmx_drp:2;
4617 		uint64_t trace:1;
4618 		uint64_t rml:1;
4619 		uint64_t twsi:1;
4620 		uint64_t reserved_44_44:1;
4621 		uint64_t pci_msi:4;
4622 		uint64_t pci_int:4;
4623 		uint64_t uart:2;
4624 		uint64_t mbox:2;
4625 		uint64_t gpio:16;
4626 		uint64_t workq:16;
4627 #else
4628 		uint64_t workq:16;
4629 		uint64_t gpio:16;
4630 		uint64_t mbox:2;
4631 		uint64_t uart:2;
4632 		uint64_t pci_int:4;
4633 		uint64_t pci_msi:4;
4634 		uint64_t reserved_44_44:1;
4635 		uint64_t twsi:1;
4636 		uint64_t rml:1;
4637 		uint64_t trace:1;
4638 		uint64_t gmx_drp:2;
4639 		uint64_t ipd_drp:1;
4640 		uint64_t reserved_51_51:1;
4641 		uint64_t timer:4;
4642 		uint64_t usb:1;
4643 		uint64_t reserved_57_57:1;
4644 		uint64_t mpi:1;
4645 		uint64_t twsi2:1;
4646 		uint64_t powiq:1;
4647 		uint64_t ipdppthr:1;
4648 		uint64_t mii:1;
4649 		uint64_t bootdma:1;
4650 #endif
4651 	} cn66xx;
4652 	struct cvmx_ciu_intx_en4_0_w1s_cnf71xx {
4653 #ifdef __BIG_ENDIAN_BITFIELD
4654 		uint64_t bootdma:1;
4655 		uint64_t reserved_62_62:1;
4656 		uint64_t ipdppthr:1;
4657 		uint64_t powiq:1;
4658 		uint64_t twsi2:1;
4659 		uint64_t mpi:1;
4660 		uint64_t pcm:1;
4661 		uint64_t usb:1;
4662 		uint64_t timer:4;
4663 		uint64_t reserved_51_51:1;
4664 		uint64_t ipd_drp:1;
4665 		uint64_t reserved_49_49:1;
4666 		uint64_t gmx_drp:1;
4667 		uint64_t trace:1;
4668 		uint64_t rml:1;
4669 		uint64_t twsi:1;
4670 		uint64_t reserved_44_44:1;
4671 		uint64_t pci_msi:4;
4672 		uint64_t pci_int:4;
4673 		uint64_t uart:2;
4674 		uint64_t mbox:2;
4675 		uint64_t gpio:16;
4676 		uint64_t workq:16;
4677 #else
4678 		uint64_t workq:16;
4679 		uint64_t gpio:16;
4680 		uint64_t mbox:2;
4681 		uint64_t uart:2;
4682 		uint64_t pci_int:4;
4683 		uint64_t pci_msi:4;
4684 		uint64_t reserved_44_44:1;
4685 		uint64_t twsi:1;
4686 		uint64_t rml:1;
4687 		uint64_t trace:1;
4688 		uint64_t gmx_drp:1;
4689 		uint64_t reserved_49_49:1;
4690 		uint64_t ipd_drp:1;
4691 		uint64_t reserved_51_51:1;
4692 		uint64_t timer:4;
4693 		uint64_t usb:1;
4694 		uint64_t pcm:1;
4695 		uint64_t mpi:1;
4696 		uint64_t twsi2:1;
4697 		uint64_t powiq:1;
4698 		uint64_t ipdppthr:1;
4699 		uint64_t reserved_62_62:1;
4700 		uint64_t bootdma:1;
4701 #endif
4702 	} cnf71xx;
4703 };
4704 
4705 union cvmx_ciu_intx_en4_1 {
4706 	uint64_t u64;
4707 	struct cvmx_ciu_intx_en4_1_s {
4708 #ifdef __BIG_ENDIAN_BITFIELD
4709 		uint64_t rst:1;
4710 		uint64_t reserved_62_62:1;
4711 		uint64_t srio3:1;
4712 		uint64_t srio2:1;
4713 		uint64_t reserved_57_59:3;
4714 		uint64_t dfm:1;
4715 		uint64_t reserved_53_55:3;
4716 		uint64_t lmc0:1;
4717 		uint64_t srio1:1;
4718 		uint64_t srio0:1;
4719 		uint64_t pem1:1;
4720 		uint64_t pem0:1;
4721 		uint64_t ptp:1;
4722 		uint64_t agl:1;
4723 		uint64_t reserved_41_45:5;
4724 		uint64_t dpi_dma:1;
4725 		uint64_t reserved_38_39:2;
4726 		uint64_t agx1:1;
4727 		uint64_t agx0:1;
4728 		uint64_t dpi:1;
4729 		uint64_t sli:1;
4730 		uint64_t usb:1;
4731 		uint64_t dfa:1;
4732 		uint64_t key:1;
4733 		uint64_t rad:1;
4734 		uint64_t tim:1;
4735 		uint64_t zip:1;
4736 		uint64_t pko:1;
4737 		uint64_t pip:1;
4738 		uint64_t ipd:1;
4739 		uint64_t l2c:1;
4740 		uint64_t pow:1;
4741 		uint64_t fpa:1;
4742 		uint64_t iob:1;
4743 		uint64_t mio:1;
4744 		uint64_t nand:1;
4745 		uint64_t mii1:1;
4746 		uint64_t usb1:1;
4747 		uint64_t uart2:1;
4748 		uint64_t wdog:16;
4749 #else
4750 		uint64_t wdog:16;
4751 		uint64_t uart2:1;
4752 		uint64_t usb1:1;
4753 		uint64_t mii1:1;
4754 		uint64_t nand:1;
4755 		uint64_t mio:1;
4756 		uint64_t iob:1;
4757 		uint64_t fpa:1;
4758 		uint64_t pow:1;
4759 		uint64_t l2c:1;
4760 		uint64_t ipd:1;
4761 		uint64_t pip:1;
4762 		uint64_t pko:1;
4763 		uint64_t zip:1;
4764 		uint64_t tim:1;
4765 		uint64_t rad:1;
4766 		uint64_t key:1;
4767 		uint64_t dfa:1;
4768 		uint64_t usb:1;
4769 		uint64_t sli:1;
4770 		uint64_t dpi:1;
4771 		uint64_t agx0:1;
4772 		uint64_t agx1:1;
4773 		uint64_t reserved_38_39:2;
4774 		uint64_t dpi_dma:1;
4775 		uint64_t reserved_41_45:5;
4776 		uint64_t agl:1;
4777 		uint64_t ptp:1;
4778 		uint64_t pem0:1;
4779 		uint64_t pem1:1;
4780 		uint64_t srio0:1;
4781 		uint64_t srio1:1;
4782 		uint64_t lmc0:1;
4783 		uint64_t reserved_53_55:3;
4784 		uint64_t dfm:1;
4785 		uint64_t reserved_57_59:3;
4786 		uint64_t srio2:1;
4787 		uint64_t srio3:1;
4788 		uint64_t reserved_62_62:1;
4789 		uint64_t rst:1;
4790 #endif
4791 	} s;
4792 	struct cvmx_ciu_intx_en4_1_cn50xx {
4793 #ifdef __BIG_ENDIAN_BITFIELD
4794 		uint64_t reserved_2_63:62;
4795 		uint64_t wdog:2;
4796 #else
4797 		uint64_t wdog:2;
4798 		uint64_t reserved_2_63:62;
4799 #endif
4800 	} cn50xx;
4801 	struct cvmx_ciu_intx_en4_1_cn52xx {
4802 #ifdef __BIG_ENDIAN_BITFIELD
4803 		uint64_t reserved_20_63:44;
4804 		uint64_t nand:1;
4805 		uint64_t mii1:1;
4806 		uint64_t usb1:1;
4807 		uint64_t uart2:1;
4808 		uint64_t reserved_4_15:12;
4809 		uint64_t wdog:4;
4810 #else
4811 		uint64_t wdog:4;
4812 		uint64_t reserved_4_15:12;
4813 		uint64_t uart2:1;
4814 		uint64_t usb1:1;
4815 		uint64_t mii1:1;
4816 		uint64_t nand:1;
4817 		uint64_t reserved_20_63:44;
4818 #endif
4819 	} cn52xx;
4820 	struct cvmx_ciu_intx_en4_1_cn52xxp1 {
4821 #ifdef __BIG_ENDIAN_BITFIELD
4822 		uint64_t reserved_19_63:45;
4823 		uint64_t mii1:1;
4824 		uint64_t usb1:1;
4825 		uint64_t uart2:1;
4826 		uint64_t reserved_4_15:12;
4827 		uint64_t wdog:4;
4828 #else
4829 		uint64_t wdog:4;
4830 		uint64_t reserved_4_15:12;
4831 		uint64_t uart2:1;
4832 		uint64_t usb1:1;
4833 		uint64_t mii1:1;
4834 		uint64_t reserved_19_63:45;
4835 #endif
4836 	} cn52xxp1;
4837 	struct cvmx_ciu_intx_en4_1_cn56xx {
4838 #ifdef __BIG_ENDIAN_BITFIELD
4839 		uint64_t reserved_12_63:52;
4840 		uint64_t wdog:12;
4841 #else
4842 		uint64_t wdog:12;
4843 		uint64_t reserved_12_63:52;
4844 #endif
4845 	} cn56xx;
4846 	struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
4847 	struct cvmx_ciu_intx_en4_1_cn58xx {
4848 #ifdef __BIG_ENDIAN_BITFIELD
4849 		uint64_t reserved_16_63:48;
4850 		uint64_t wdog:16;
4851 #else
4852 		uint64_t wdog:16;
4853 		uint64_t reserved_16_63:48;
4854 #endif
4855 	} cn58xx;
4856 	struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
4857 	struct cvmx_ciu_intx_en4_1_cn61xx {
4858 #ifdef __BIG_ENDIAN_BITFIELD
4859 		uint64_t rst:1;
4860 		uint64_t reserved_53_62:10;
4861 		uint64_t lmc0:1;
4862 		uint64_t reserved_50_51:2;
4863 		uint64_t pem1:1;
4864 		uint64_t pem0:1;
4865 		uint64_t ptp:1;
4866 		uint64_t agl:1;
4867 		uint64_t reserved_41_45:5;
4868 		uint64_t dpi_dma:1;
4869 		uint64_t reserved_38_39:2;
4870 		uint64_t agx1:1;
4871 		uint64_t agx0:1;
4872 		uint64_t dpi:1;
4873 		uint64_t sli:1;
4874 		uint64_t usb:1;
4875 		uint64_t dfa:1;
4876 		uint64_t key:1;
4877 		uint64_t rad:1;
4878 		uint64_t tim:1;
4879 		uint64_t zip:1;
4880 		uint64_t pko:1;
4881 		uint64_t pip:1;
4882 		uint64_t ipd:1;
4883 		uint64_t l2c:1;
4884 		uint64_t pow:1;
4885 		uint64_t fpa:1;
4886 		uint64_t iob:1;
4887 		uint64_t mio:1;
4888 		uint64_t nand:1;
4889 		uint64_t mii1:1;
4890 		uint64_t reserved_4_17:14;
4891 		uint64_t wdog:4;
4892 #else
4893 		uint64_t wdog:4;
4894 		uint64_t reserved_4_17:14;
4895 		uint64_t mii1:1;
4896 		uint64_t nand:1;
4897 		uint64_t mio:1;
4898 		uint64_t iob:1;
4899 		uint64_t fpa:1;
4900 		uint64_t pow:1;
4901 		uint64_t l2c:1;
4902 		uint64_t ipd:1;
4903 		uint64_t pip:1;
4904 		uint64_t pko:1;
4905 		uint64_t zip:1;
4906 		uint64_t tim:1;
4907 		uint64_t rad:1;
4908 		uint64_t key:1;
4909 		uint64_t dfa:1;
4910 		uint64_t usb:1;
4911 		uint64_t sli:1;
4912 		uint64_t dpi:1;
4913 		uint64_t agx0:1;
4914 		uint64_t agx1:1;
4915 		uint64_t reserved_38_39:2;
4916 		uint64_t dpi_dma:1;
4917 		uint64_t reserved_41_45:5;
4918 		uint64_t agl:1;
4919 		uint64_t ptp:1;
4920 		uint64_t pem0:1;
4921 		uint64_t pem1:1;
4922 		uint64_t reserved_50_51:2;
4923 		uint64_t lmc0:1;
4924 		uint64_t reserved_53_62:10;
4925 		uint64_t rst:1;
4926 #endif
4927 	} cn61xx;
4928 	struct cvmx_ciu_intx_en4_1_cn63xx {
4929 #ifdef __BIG_ENDIAN_BITFIELD
4930 		uint64_t rst:1;
4931 		uint64_t reserved_57_62:6;
4932 		uint64_t dfm:1;
4933 		uint64_t reserved_53_55:3;
4934 		uint64_t lmc0:1;
4935 		uint64_t srio1:1;
4936 		uint64_t srio0:1;
4937 		uint64_t pem1:1;
4938 		uint64_t pem0:1;
4939 		uint64_t ptp:1;
4940 		uint64_t agl:1;
4941 		uint64_t reserved_37_45:9;
4942 		uint64_t agx0:1;
4943 		uint64_t dpi:1;
4944 		uint64_t sli:1;
4945 		uint64_t usb:1;
4946 		uint64_t dfa:1;
4947 		uint64_t key:1;
4948 		uint64_t rad:1;
4949 		uint64_t tim:1;
4950 		uint64_t zip:1;
4951 		uint64_t pko:1;
4952 		uint64_t pip:1;
4953 		uint64_t ipd:1;
4954 		uint64_t l2c:1;
4955 		uint64_t pow:1;
4956 		uint64_t fpa:1;
4957 		uint64_t iob:1;
4958 		uint64_t mio:1;
4959 		uint64_t nand:1;
4960 		uint64_t mii1:1;
4961 		uint64_t reserved_6_17:12;
4962 		uint64_t wdog:6;
4963 #else
4964 		uint64_t wdog:6;
4965 		uint64_t reserved_6_17:12;
4966 		uint64_t mii1:1;
4967 		uint64_t nand:1;
4968 		uint64_t mio:1;
4969 		uint64_t iob:1;
4970 		uint64_t fpa:1;
4971 		uint64_t pow:1;
4972 		uint64_t l2c:1;
4973 		uint64_t ipd:1;
4974 		uint64_t pip:1;
4975 		uint64_t pko:1;
4976 		uint64_t zip:1;
4977 		uint64_t tim:1;
4978 		uint64_t rad:1;
4979 		uint64_t key:1;
4980 		uint64_t dfa:1;
4981 		uint64_t usb:1;
4982 		uint64_t sli:1;
4983 		uint64_t dpi:1;
4984 		uint64_t agx0:1;
4985 		uint64_t reserved_37_45:9;
4986 		uint64_t agl:1;
4987 		uint64_t ptp:1;
4988 		uint64_t pem0:1;
4989 		uint64_t pem1:1;
4990 		uint64_t srio0:1;
4991 		uint64_t srio1:1;
4992 		uint64_t lmc0:1;
4993 		uint64_t reserved_53_55:3;
4994 		uint64_t dfm:1;
4995 		uint64_t reserved_57_62:6;
4996 		uint64_t rst:1;
4997 #endif
4998 	} cn63xx;
4999 	struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
5000 	struct cvmx_ciu_intx_en4_1_cn66xx {
5001 #ifdef __BIG_ENDIAN_BITFIELD
5002 		uint64_t rst:1;
5003 		uint64_t reserved_62_62:1;
5004 		uint64_t srio3:1;
5005 		uint64_t srio2:1;
5006 		uint64_t reserved_57_59:3;
5007 		uint64_t dfm:1;
5008 		uint64_t reserved_53_55:3;
5009 		uint64_t lmc0:1;
5010 		uint64_t reserved_51_51:1;
5011 		uint64_t srio0:1;
5012 		uint64_t pem1:1;
5013 		uint64_t pem0:1;
5014 		uint64_t ptp:1;
5015 		uint64_t agl:1;
5016 		uint64_t reserved_38_45:8;
5017 		uint64_t agx1:1;
5018 		uint64_t agx0:1;
5019 		uint64_t dpi:1;
5020 		uint64_t sli:1;
5021 		uint64_t usb:1;
5022 		uint64_t dfa:1;
5023 		uint64_t key:1;
5024 		uint64_t rad:1;
5025 		uint64_t tim:1;
5026 		uint64_t zip:1;
5027 		uint64_t pko:1;
5028 		uint64_t pip:1;
5029 		uint64_t ipd:1;
5030 		uint64_t l2c:1;
5031 		uint64_t pow:1;
5032 		uint64_t fpa:1;
5033 		uint64_t iob:1;
5034 		uint64_t mio:1;
5035 		uint64_t nand:1;
5036 		uint64_t mii1:1;
5037 		uint64_t reserved_10_17:8;
5038 		uint64_t wdog:10;
5039 #else
5040 		uint64_t wdog:10;
5041 		uint64_t reserved_10_17:8;
5042 		uint64_t mii1:1;
5043 		uint64_t nand:1;
5044 		uint64_t mio:1;
5045 		uint64_t iob:1;
5046 		uint64_t fpa:1;
5047 		uint64_t pow:1;
5048 		uint64_t l2c:1;
5049 		uint64_t ipd:1;
5050 		uint64_t pip:1;
5051 		uint64_t pko:1;
5052 		uint64_t zip:1;
5053 		uint64_t tim:1;
5054 		uint64_t rad:1;
5055 		uint64_t key:1;
5056 		uint64_t dfa:1;
5057 		uint64_t usb:1;
5058 		uint64_t sli:1;
5059 		uint64_t dpi:1;
5060 		uint64_t agx0:1;
5061 		uint64_t agx1:1;
5062 		uint64_t reserved_38_45:8;
5063 		uint64_t agl:1;
5064 		uint64_t ptp:1;
5065 		uint64_t pem0:1;
5066 		uint64_t pem1:1;
5067 		uint64_t srio0:1;
5068 		uint64_t reserved_51_51:1;
5069 		uint64_t lmc0:1;
5070 		uint64_t reserved_53_55:3;
5071 		uint64_t dfm:1;
5072 		uint64_t reserved_57_59:3;
5073 		uint64_t srio2:1;
5074 		uint64_t srio3:1;
5075 		uint64_t reserved_62_62:1;
5076 		uint64_t rst:1;
5077 #endif
5078 	} cn66xx;
5079 	struct cvmx_ciu_intx_en4_1_cnf71xx {
5080 #ifdef __BIG_ENDIAN_BITFIELD
5081 		uint64_t rst:1;
5082 		uint64_t reserved_53_62:10;
5083 		uint64_t lmc0:1;
5084 		uint64_t reserved_50_51:2;
5085 		uint64_t pem1:1;
5086 		uint64_t pem0:1;
5087 		uint64_t ptp:1;
5088 		uint64_t reserved_41_46:6;
5089 		uint64_t dpi_dma:1;
5090 		uint64_t reserved_37_39:3;
5091 		uint64_t agx0:1;
5092 		uint64_t dpi:1;
5093 		uint64_t sli:1;
5094 		uint64_t usb:1;
5095 		uint64_t reserved_32_32:1;
5096 		uint64_t key:1;
5097 		uint64_t rad:1;
5098 		uint64_t tim:1;
5099 		uint64_t reserved_28_28:1;
5100 		uint64_t pko:1;
5101 		uint64_t pip:1;
5102 		uint64_t ipd:1;
5103 		uint64_t l2c:1;
5104 		uint64_t pow:1;
5105 		uint64_t fpa:1;
5106 		uint64_t iob:1;
5107 		uint64_t mio:1;
5108 		uint64_t nand:1;
5109 		uint64_t reserved_4_18:15;
5110 		uint64_t wdog:4;
5111 #else
5112 		uint64_t wdog:4;
5113 		uint64_t reserved_4_18:15;
5114 		uint64_t nand:1;
5115 		uint64_t mio:1;
5116 		uint64_t iob:1;
5117 		uint64_t fpa:1;
5118 		uint64_t pow:1;
5119 		uint64_t l2c:1;
5120 		uint64_t ipd:1;
5121 		uint64_t pip:1;
5122 		uint64_t pko:1;
5123 		uint64_t reserved_28_28:1;
5124 		uint64_t tim:1;
5125 		uint64_t rad:1;
5126 		uint64_t key:1;
5127 		uint64_t reserved_32_32:1;
5128 		uint64_t usb:1;
5129 		uint64_t sli:1;
5130 		uint64_t dpi:1;
5131 		uint64_t agx0:1;
5132 		uint64_t reserved_37_39:3;
5133 		uint64_t dpi_dma:1;
5134 		uint64_t reserved_41_46:6;
5135 		uint64_t ptp:1;
5136 		uint64_t pem0:1;
5137 		uint64_t pem1:1;
5138 		uint64_t reserved_50_51:2;
5139 		uint64_t lmc0:1;
5140 		uint64_t reserved_53_62:10;
5141 		uint64_t rst:1;
5142 #endif
5143 	} cnf71xx;
5144 };
5145 
5146 union cvmx_ciu_intx_en4_1_w1c {
5147 	uint64_t u64;
5148 	struct cvmx_ciu_intx_en4_1_w1c_s {
5149 #ifdef __BIG_ENDIAN_BITFIELD
5150 		uint64_t rst:1;
5151 		uint64_t reserved_62_62:1;
5152 		uint64_t srio3:1;
5153 		uint64_t srio2:1;
5154 		uint64_t reserved_57_59:3;
5155 		uint64_t dfm:1;
5156 		uint64_t reserved_53_55:3;
5157 		uint64_t lmc0:1;
5158 		uint64_t srio1:1;
5159 		uint64_t srio0:1;
5160 		uint64_t pem1:1;
5161 		uint64_t pem0:1;
5162 		uint64_t ptp:1;
5163 		uint64_t agl:1;
5164 		uint64_t reserved_41_45:5;
5165 		uint64_t dpi_dma:1;
5166 		uint64_t reserved_38_39:2;
5167 		uint64_t agx1:1;
5168 		uint64_t agx0:1;
5169 		uint64_t dpi:1;
5170 		uint64_t sli:1;
5171 		uint64_t usb:1;
5172 		uint64_t dfa:1;
5173 		uint64_t key:1;
5174 		uint64_t rad:1;
5175 		uint64_t tim:1;
5176 		uint64_t zip:1;
5177 		uint64_t pko:1;
5178 		uint64_t pip:1;
5179 		uint64_t ipd:1;
5180 		uint64_t l2c:1;
5181 		uint64_t pow:1;
5182 		uint64_t fpa:1;
5183 		uint64_t iob:1;
5184 		uint64_t mio:1;
5185 		uint64_t nand:1;
5186 		uint64_t mii1:1;
5187 		uint64_t usb1:1;
5188 		uint64_t uart2:1;
5189 		uint64_t wdog:16;
5190 #else
5191 		uint64_t wdog:16;
5192 		uint64_t uart2:1;
5193 		uint64_t usb1:1;
5194 		uint64_t mii1:1;
5195 		uint64_t nand:1;
5196 		uint64_t mio:1;
5197 		uint64_t iob:1;
5198 		uint64_t fpa:1;
5199 		uint64_t pow:1;
5200 		uint64_t l2c:1;
5201 		uint64_t ipd:1;
5202 		uint64_t pip:1;
5203 		uint64_t pko:1;
5204 		uint64_t zip:1;
5205 		uint64_t tim:1;
5206 		uint64_t rad:1;
5207 		uint64_t key:1;
5208 		uint64_t dfa:1;
5209 		uint64_t usb:1;
5210 		uint64_t sli:1;
5211 		uint64_t dpi:1;
5212 		uint64_t agx0:1;
5213 		uint64_t agx1:1;
5214 		uint64_t reserved_38_39:2;
5215 		uint64_t dpi_dma:1;
5216 		uint64_t reserved_41_45:5;
5217 		uint64_t agl:1;
5218 		uint64_t ptp:1;
5219 		uint64_t pem0:1;
5220 		uint64_t pem1:1;
5221 		uint64_t srio0:1;
5222 		uint64_t srio1:1;
5223 		uint64_t lmc0:1;
5224 		uint64_t reserved_53_55:3;
5225 		uint64_t dfm:1;
5226 		uint64_t reserved_57_59:3;
5227 		uint64_t srio2:1;
5228 		uint64_t srio3:1;
5229 		uint64_t reserved_62_62:1;
5230 		uint64_t rst:1;
5231 #endif
5232 	} s;
5233 	struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
5234 #ifdef __BIG_ENDIAN_BITFIELD
5235 		uint64_t reserved_20_63:44;
5236 		uint64_t nand:1;
5237 		uint64_t mii1:1;
5238 		uint64_t usb1:1;
5239 		uint64_t uart2:1;
5240 		uint64_t reserved_4_15:12;
5241 		uint64_t wdog:4;
5242 #else
5243 		uint64_t wdog:4;
5244 		uint64_t reserved_4_15:12;
5245 		uint64_t uart2:1;
5246 		uint64_t usb1:1;
5247 		uint64_t mii1:1;
5248 		uint64_t nand:1;
5249 		uint64_t reserved_20_63:44;
5250 #endif
5251 	} cn52xx;
5252 	struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
5253 #ifdef __BIG_ENDIAN_BITFIELD
5254 		uint64_t reserved_12_63:52;
5255 		uint64_t wdog:12;
5256 #else
5257 		uint64_t wdog:12;
5258 		uint64_t reserved_12_63:52;
5259 #endif
5260 	} cn56xx;
5261 	struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
5262 #ifdef __BIG_ENDIAN_BITFIELD
5263 		uint64_t reserved_16_63:48;
5264 		uint64_t wdog:16;
5265 #else
5266 		uint64_t wdog:16;
5267 		uint64_t reserved_16_63:48;
5268 #endif
5269 	} cn58xx;
5270 	struct cvmx_ciu_intx_en4_1_w1c_cn61xx {
5271 #ifdef __BIG_ENDIAN_BITFIELD
5272 		uint64_t rst:1;
5273 		uint64_t reserved_53_62:10;
5274 		uint64_t lmc0:1;
5275 		uint64_t reserved_50_51:2;
5276 		uint64_t pem1:1;
5277 		uint64_t pem0:1;
5278 		uint64_t ptp:1;
5279 		uint64_t agl:1;
5280 		uint64_t reserved_41_45:5;
5281 		uint64_t dpi_dma:1;
5282 		uint64_t reserved_38_39:2;
5283 		uint64_t agx1:1;
5284 		uint64_t agx0:1;
5285 		uint64_t dpi:1;
5286 		uint64_t sli:1;
5287 		uint64_t usb:1;
5288 		uint64_t dfa:1;
5289 		uint64_t key:1;
5290 		uint64_t rad:1;
5291 		uint64_t tim:1;
5292 		uint64_t zip:1;
5293 		uint64_t pko:1;
5294 		uint64_t pip:1;
5295 		uint64_t ipd:1;
5296 		uint64_t l2c:1;
5297 		uint64_t pow:1;
5298 		uint64_t fpa:1;
5299 		uint64_t iob:1;
5300 		uint64_t mio:1;
5301 		uint64_t nand:1;
5302 		uint64_t mii1:1;
5303 		uint64_t reserved_4_17:14;
5304 		uint64_t wdog:4;
5305 #else
5306 		uint64_t wdog:4;
5307 		uint64_t reserved_4_17:14;
5308 		uint64_t mii1:1;
5309 		uint64_t nand:1;
5310 		uint64_t mio:1;
5311 		uint64_t iob:1;
5312 		uint64_t fpa:1;
5313 		uint64_t pow:1;
5314 		uint64_t l2c:1;
5315 		uint64_t ipd:1;
5316 		uint64_t pip:1;
5317 		uint64_t pko:1;
5318 		uint64_t zip:1;
5319 		uint64_t tim:1;
5320 		uint64_t rad:1;
5321 		uint64_t key:1;
5322 		uint64_t dfa:1;
5323 		uint64_t usb:1;
5324 		uint64_t sli:1;
5325 		uint64_t dpi:1;
5326 		uint64_t agx0:1;
5327 		uint64_t agx1:1;
5328 		uint64_t reserved_38_39:2;
5329 		uint64_t dpi_dma:1;
5330 		uint64_t reserved_41_45:5;
5331 		uint64_t agl:1;
5332 		uint64_t ptp:1;
5333 		uint64_t pem0:1;
5334 		uint64_t pem1:1;
5335 		uint64_t reserved_50_51:2;
5336 		uint64_t lmc0:1;
5337 		uint64_t reserved_53_62:10;
5338 		uint64_t rst:1;
5339 #endif
5340 	} cn61xx;
5341 	struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
5342 #ifdef __BIG_ENDIAN_BITFIELD
5343 		uint64_t rst:1;
5344 		uint64_t reserved_57_62:6;
5345 		uint64_t dfm:1;
5346 		uint64_t reserved_53_55:3;
5347 		uint64_t lmc0:1;
5348 		uint64_t srio1:1;
5349 		uint64_t srio0:1;
5350 		uint64_t pem1:1;
5351 		uint64_t pem0:1;
5352 		uint64_t ptp:1;
5353 		uint64_t agl:1;
5354 		uint64_t reserved_37_45:9;
5355 		uint64_t agx0:1;
5356 		uint64_t dpi:1;
5357 		uint64_t sli:1;
5358 		uint64_t usb:1;
5359 		uint64_t dfa:1;
5360 		uint64_t key:1;
5361 		uint64_t rad:1;
5362 		uint64_t tim:1;
5363 		uint64_t zip:1;
5364 		uint64_t pko:1;
5365 		uint64_t pip:1;
5366 		uint64_t ipd:1;
5367 		uint64_t l2c:1;
5368 		uint64_t pow:1;
5369 		uint64_t fpa:1;
5370 		uint64_t iob:1;
5371 		uint64_t mio:1;
5372 		uint64_t nand:1;
5373 		uint64_t mii1:1;
5374 		uint64_t reserved_6_17:12;
5375 		uint64_t wdog:6;
5376 #else
5377 		uint64_t wdog:6;
5378 		uint64_t reserved_6_17:12;
5379 		uint64_t mii1:1;
5380 		uint64_t nand:1;
5381 		uint64_t mio:1;
5382 		uint64_t iob:1;
5383 		uint64_t fpa:1;
5384 		uint64_t pow:1;
5385 		uint64_t l2c:1;
5386 		uint64_t ipd:1;
5387 		uint64_t pip:1;
5388 		uint64_t pko:1;
5389 		uint64_t zip:1;
5390 		uint64_t tim:1;
5391 		uint64_t rad:1;
5392 		uint64_t key:1;
5393 		uint64_t dfa:1;
5394 		uint64_t usb:1;
5395 		uint64_t sli:1;
5396 		uint64_t dpi:1;
5397 		uint64_t agx0:1;
5398 		uint64_t reserved_37_45:9;
5399 		uint64_t agl:1;
5400 		uint64_t ptp:1;
5401 		uint64_t pem0:1;
5402 		uint64_t pem1:1;
5403 		uint64_t srio0:1;
5404 		uint64_t srio1:1;
5405 		uint64_t lmc0:1;
5406 		uint64_t reserved_53_55:3;
5407 		uint64_t dfm:1;
5408 		uint64_t reserved_57_62:6;
5409 		uint64_t rst:1;
5410 #endif
5411 	} cn63xx;
5412 	struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
5413 	struct cvmx_ciu_intx_en4_1_w1c_cn66xx {
5414 #ifdef __BIG_ENDIAN_BITFIELD
5415 		uint64_t rst:1;
5416 		uint64_t reserved_62_62:1;
5417 		uint64_t srio3:1;
5418 		uint64_t srio2:1;
5419 		uint64_t reserved_57_59:3;
5420 		uint64_t dfm:1;
5421 		uint64_t reserved_53_55:3;
5422 		uint64_t lmc0:1;
5423 		uint64_t reserved_51_51:1;
5424 		uint64_t srio0:1;
5425 		uint64_t pem1:1;
5426 		uint64_t pem0:1;
5427 		uint64_t ptp:1;
5428 		uint64_t agl:1;
5429 		uint64_t reserved_38_45:8;
5430 		uint64_t agx1:1;
5431 		uint64_t agx0:1;
5432 		uint64_t dpi:1;
5433 		uint64_t sli:1;
5434 		uint64_t usb:1;
5435 		uint64_t dfa:1;
5436 		uint64_t key:1;
5437 		uint64_t rad:1;
5438 		uint64_t tim:1;
5439 		uint64_t zip:1;
5440 		uint64_t pko:1;
5441 		uint64_t pip:1;
5442 		uint64_t ipd:1;
5443 		uint64_t l2c:1;
5444 		uint64_t pow:1;
5445 		uint64_t fpa:1;
5446 		uint64_t iob:1;
5447 		uint64_t mio:1;
5448 		uint64_t nand:1;
5449 		uint64_t mii1:1;
5450 		uint64_t reserved_10_17:8;
5451 		uint64_t wdog:10;
5452 #else
5453 		uint64_t wdog:10;
5454 		uint64_t reserved_10_17:8;
5455 		uint64_t mii1:1;
5456 		uint64_t nand:1;
5457 		uint64_t mio:1;
5458 		uint64_t iob:1;
5459 		uint64_t fpa:1;
5460 		uint64_t pow:1;
5461 		uint64_t l2c:1;
5462 		uint64_t ipd:1;
5463 		uint64_t pip:1;
5464 		uint64_t pko:1;
5465 		uint64_t zip:1;
5466 		uint64_t tim:1;
5467 		uint64_t rad:1;
5468 		uint64_t key:1;
5469 		uint64_t dfa:1;
5470 		uint64_t usb:1;
5471 		uint64_t sli:1;
5472 		uint64_t dpi:1;
5473 		uint64_t agx0:1;
5474 		uint64_t agx1:1;
5475 		uint64_t reserved_38_45:8;
5476 		uint64_t agl:1;
5477 		uint64_t ptp:1;
5478 		uint64_t pem0:1;
5479 		uint64_t pem1:1;
5480 		uint64_t srio0:1;
5481 		uint64_t reserved_51_51:1;
5482 		uint64_t lmc0:1;
5483 		uint64_t reserved_53_55:3;
5484 		uint64_t dfm:1;
5485 		uint64_t reserved_57_59:3;
5486 		uint64_t srio2:1;
5487 		uint64_t srio3:1;
5488 		uint64_t reserved_62_62:1;
5489 		uint64_t rst:1;
5490 #endif
5491 	} cn66xx;
5492 	struct cvmx_ciu_intx_en4_1_w1c_cnf71xx {
5493 #ifdef __BIG_ENDIAN_BITFIELD
5494 		uint64_t rst:1;
5495 		uint64_t reserved_53_62:10;
5496 		uint64_t lmc0:1;
5497 		uint64_t reserved_50_51:2;
5498 		uint64_t pem1:1;
5499 		uint64_t pem0:1;
5500 		uint64_t ptp:1;
5501 		uint64_t reserved_41_46:6;
5502 		uint64_t dpi_dma:1;
5503 		uint64_t reserved_37_39:3;
5504 		uint64_t agx0:1;
5505 		uint64_t dpi:1;
5506 		uint64_t sli:1;
5507 		uint64_t usb:1;
5508 		uint64_t reserved_32_32:1;
5509 		uint64_t key:1;
5510 		uint64_t rad:1;
5511 		uint64_t tim:1;
5512 		uint64_t reserved_28_28:1;
5513 		uint64_t pko:1;
5514 		uint64_t pip:1;
5515 		uint64_t ipd:1;
5516 		uint64_t l2c:1;
5517 		uint64_t pow:1;
5518 		uint64_t fpa:1;
5519 		uint64_t iob:1;
5520 		uint64_t mio:1;
5521 		uint64_t nand:1;
5522 		uint64_t reserved_4_18:15;
5523 		uint64_t wdog:4;
5524 #else
5525 		uint64_t wdog:4;
5526 		uint64_t reserved_4_18:15;
5527 		uint64_t nand:1;
5528 		uint64_t mio:1;
5529 		uint64_t iob:1;
5530 		uint64_t fpa:1;
5531 		uint64_t pow:1;
5532 		uint64_t l2c:1;
5533 		uint64_t ipd:1;
5534 		uint64_t pip:1;
5535 		uint64_t pko:1;
5536 		uint64_t reserved_28_28:1;
5537 		uint64_t tim:1;
5538 		uint64_t rad:1;
5539 		uint64_t key:1;
5540 		uint64_t reserved_32_32:1;
5541 		uint64_t usb:1;
5542 		uint64_t sli:1;
5543 		uint64_t dpi:1;
5544 		uint64_t agx0:1;
5545 		uint64_t reserved_37_39:3;
5546 		uint64_t dpi_dma:1;
5547 		uint64_t reserved_41_46:6;
5548 		uint64_t ptp:1;
5549 		uint64_t pem0:1;
5550 		uint64_t pem1:1;
5551 		uint64_t reserved_50_51:2;
5552 		uint64_t lmc0:1;
5553 		uint64_t reserved_53_62:10;
5554 		uint64_t rst:1;
5555 #endif
5556 	} cnf71xx;
5557 };
5558 
5559 union cvmx_ciu_intx_en4_1_w1s {
5560 	uint64_t u64;
5561 	struct cvmx_ciu_intx_en4_1_w1s_s {
5562 #ifdef __BIG_ENDIAN_BITFIELD
5563 		uint64_t rst:1;
5564 		uint64_t reserved_62_62:1;
5565 		uint64_t srio3:1;
5566 		uint64_t srio2:1;
5567 		uint64_t reserved_57_59:3;
5568 		uint64_t dfm:1;
5569 		uint64_t reserved_53_55:3;
5570 		uint64_t lmc0:1;
5571 		uint64_t srio1:1;
5572 		uint64_t srio0:1;
5573 		uint64_t pem1:1;
5574 		uint64_t pem0:1;
5575 		uint64_t ptp:1;
5576 		uint64_t agl:1;
5577 		uint64_t reserved_41_45:5;
5578 		uint64_t dpi_dma:1;
5579 		uint64_t reserved_38_39:2;
5580 		uint64_t agx1:1;
5581 		uint64_t agx0:1;
5582 		uint64_t dpi:1;
5583 		uint64_t sli:1;
5584 		uint64_t usb:1;
5585 		uint64_t dfa:1;
5586 		uint64_t key:1;
5587 		uint64_t rad:1;
5588 		uint64_t tim:1;
5589 		uint64_t zip:1;
5590 		uint64_t pko:1;
5591 		uint64_t pip:1;
5592 		uint64_t ipd:1;
5593 		uint64_t l2c:1;
5594 		uint64_t pow:1;
5595 		uint64_t fpa:1;
5596 		uint64_t iob:1;
5597 		uint64_t mio:1;
5598 		uint64_t nand:1;
5599 		uint64_t mii1:1;
5600 		uint64_t usb1:1;
5601 		uint64_t uart2:1;
5602 		uint64_t wdog:16;
5603 #else
5604 		uint64_t wdog:16;
5605 		uint64_t uart2:1;
5606 		uint64_t usb1:1;
5607 		uint64_t mii1:1;
5608 		uint64_t nand:1;
5609 		uint64_t mio:1;
5610 		uint64_t iob:1;
5611 		uint64_t fpa:1;
5612 		uint64_t pow:1;
5613 		uint64_t l2c:1;
5614 		uint64_t ipd:1;
5615 		uint64_t pip:1;
5616 		uint64_t pko:1;
5617 		uint64_t zip:1;
5618 		uint64_t tim:1;
5619 		uint64_t rad:1;
5620 		uint64_t key:1;
5621 		uint64_t dfa:1;
5622 		uint64_t usb:1;
5623 		uint64_t sli:1;
5624 		uint64_t dpi:1;
5625 		uint64_t agx0:1;
5626 		uint64_t agx1:1;
5627 		uint64_t reserved_38_39:2;
5628 		uint64_t dpi_dma:1;
5629 		uint64_t reserved_41_45:5;
5630 		uint64_t agl:1;
5631 		uint64_t ptp:1;
5632 		uint64_t pem0:1;
5633 		uint64_t pem1:1;
5634 		uint64_t srio0:1;
5635 		uint64_t srio1:1;
5636 		uint64_t lmc0:1;
5637 		uint64_t reserved_53_55:3;
5638 		uint64_t dfm:1;
5639 		uint64_t reserved_57_59:3;
5640 		uint64_t srio2:1;
5641 		uint64_t srio3:1;
5642 		uint64_t reserved_62_62:1;
5643 		uint64_t rst:1;
5644 #endif
5645 	} s;
5646 	struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
5647 #ifdef __BIG_ENDIAN_BITFIELD
5648 		uint64_t reserved_20_63:44;
5649 		uint64_t nand:1;
5650 		uint64_t mii1:1;
5651 		uint64_t usb1:1;
5652 		uint64_t uart2:1;
5653 		uint64_t reserved_4_15:12;
5654 		uint64_t wdog:4;
5655 #else
5656 		uint64_t wdog:4;
5657 		uint64_t reserved_4_15:12;
5658 		uint64_t uart2:1;
5659 		uint64_t usb1:1;
5660 		uint64_t mii1:1;
5661 		uint64_t nand:1;
5662 		uint64_t reserved_20_63:44;
5663 #endif
5664 	} cn52xx;
5665 	struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
5666 #ifdef __BIG_ENDIAN_BITFIELD
5667 		uint64_t reserved_12_63:52;
5668 		uint64_t wdog:12;
5669 #else
5670 		uint64_t wdog:12;
5671 		uint64_t reserved_12_63:52;
5672 #endif
5673 	} cn56xx;
5674 	struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
5675 #ifdef __BIG_ENDIAN_BITFIELD
5676 		uint64_t reserved_16_63:48;
5677 		uint64_t wdog:16;
5678 #else
5679 		uint64_t wdog:16;
5680 		uint64_t reserved_16_63:48;
5681 #endif
5682 	} cn58xx;
5683 	struct cvmx_ciu_intx_en4_1_w1s_cn61xx {
5684 #ifdef __BIG_ENDIAN_BITFIELD
5685 		uint64_t rst:1;
5686 		uint64_t reserved_53_62:10;
5687 		uint64_t lmc0:1;
5688 		uint64_t reserved_50_51:2;
5689 		uint64_t pem1:1;
5690 		uint64_t pem0:1;
5691 		uint64_t ptp:1;
5692 		uint64_t agl:1;
5693 		uint64_t reserved_41_45:5;
5694 		uint64_t dpi_dma:1;
5695 		uint64_t reserved_38_39:2;
5696 		uint64_t agx1:1;
5697 		uint64_t agx0:1;
5698 		uint64_t dpi:1;
5699 		uint64_t sli:1;
5700 		uint64_t usb:1;
5701 		uint64_t dfa:1;
5702 		uint64_t key:1;
5703 		uint64_t rad:1;
5704 		uint64_t tim:1;
5705 		uint64_t zip:1;
5706 		uint64_t pko:1;
5707 		uint64_t pip:1;
5708 		uint64_t ipd:1;
5709 		uint64_t l2c:1;
5710 		uint64_t pow:1;
5711 		uint64_t fpa:1;
5712 		uint64_t iob:1;
5713 		uint64_t mio:1;
5714 		uint64_t nand:1;
5715 		uint64_t mii1:1;
5716 		uint64_t reserved_4_17:14;
5717 		uint64_t wdog:4;
5718 #else
5719 		uint64_t wdog:4;
5720 		uint64_t reserved_4_17:14;
5721 		uint64_t mii1:1;
5722 		uint64_t nand:1;
5723 		uint64_t mio:1;
5724 		uint64_t iob:1;
5725 		uint64_t fpa:1;
5726 		uint64_t pow:1;
5727 		uint64_t l2c:1;
5728 		uint64_t ipd:1;
5729 		uint64_t pip:1;
5730 		uint64_t pko:1;
5731 		uint64_t zip:1;
5732 		uint64_t tim:1;
5733 		uint64_t rad:1;
5734 		uint64_t key:1;
5735 		uint64_t dfa:1;
5736 		uint64_t usb:1;
5737 		uint64_t sli:1;
5738 		uint64_t dpi:1;
5739 		uint64_t agx0:1;
5740 		uint64_t agx1:1;
5741 		uint64_t reserved_38_39:2;
5742 		uint64_t dpi_dma:1;
5743 		uint64_t reserved_41_45:5;
5744 		uint64_t agl:1;
5745 		uint64_t ptp:1;
5746 		uint64_t pem0:1;
5747 		uint64_t pem1:1;
5748 		uint64_t reserved_50_51:2;
5749 		uint64_t lmc0:1;
5750 		uint64_t reserved_53_62:10;
5751 		uint64_t rst:1;
5752 #endif
5753 	} cn61xx;
5754 	struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
5755 #ifdef __BIG_ENDIAN_BITFIELD
5756 		uint64_t rst:1;
5757 		uint64_t reserved_57_62:6;
5758 		uint64_t dfm:1;
5759 		uint64_t reserved_53_55:3;
5760 		uint64_t lmc0:1;
5761 		uint64_t srio1:1;
5762 		uint64_t srio0:1;
5763 		uint64_t pem1:1;
5764 		uint64_t pem0:1;
5765 		uint64_t ptp:1;
5766 		uint64_t agl:1;
5767 		uint64_t reserved_37_45:9;
5768 		uint64_t agx0:1;
5769 		uint64_t dpi:1;
5770 		uint64_t sli:1;
5771 		uint64_t usb:1;
5772 		uint64_t dfa:1;
5773 		uint64_t key:1;
5774 		uint64_t rad:1;
5775 		uint64_t tim:1;
5776 		uint64_t zip:1;
5777 		uint64_t pko:1;
5778 		uint64_t pip:1;
5779 		uint64_t ipd:1;
5780 		uint64_t l2c:1;
5781 		uint64_t pow:1;
5782 		uint64_t fpa:1;
5783 		uint64_t iob:1;
5784 		uint64_t mio:1;
5785 		uint64_t nand:1;
5786 		uint64_t mii1:1;
5787 		uint64_t reserved_6_17:12;
5788 		uint64_t wdog:6;
5789 #else
5790 		uint64_t wdog:6;
5791 		uint64_t reserved_6_17:12;
5792 		uint64_t mii1:1;
5793 		uint64_t nand:1;
5794 		uint64_t mio:1;
5795 		uint64_t iob:1;
5796 		uint64_t fpa:1;
5797 		uint64_t pow:1;
5798 		uint64_t l2c:1;
5799 		uint64_t ipd:1;
5800 		uint64_t pip:1;
5801 		uint64_t pko:1;
5802 		uint64_t zip:1;
5803 		uint64_t tim:1;
5804 		uint64_t rad:1;
5805 		uint64_t key:1;
5806 		uint64_t dfa:1;
5807 		uint64_t usb:1;
5808 		uint64_t sli:1;
5809 		uint64_t dpi:1;
5810 		uint64_t agx0:1;
5811 		uint64_t reserved_37_45:9;
5812 		uint64_t agl:1;
5813 		uint64_t ptp:1;
5814 		uint64_t pem0:1;
5815 		uint64_t pem1:1;
5816 		uint64_t srio0:1;
5817 		uint64_t srio1:1;
5818 		uint64_t lmc0:1;
5819 		uint64_t reserved_53_55:3;
5820 		uint64_t dfm:1;
5821 		uint64_t reserved_57_62:6;
5822 		uint64_t rst:1;
5823 #endif
5824 	} cn63xx;
5825 	struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
5826 	struct cvmx_ciu_intx_en4_1_w1s_cn66xx {
5827 #ifdef __BIG_ENDIAN_BITFIELD
5828 		uint64_t rst:1;
5829 		uint64_t reserved_62_62:1;
5830 		uint64_t srio3:1;
5831 		uint64_t srio2:1;
5832 		uint64_t reserved_57_59:3;
5833 		uint64_t dfm:1;
5834 		uint64_t reserved_53_55:3;
5835 		uint64_t lmc0:1;
5836 		uint64_t reserved_51_51:1;
5837 		uint64_t srio0:1;
5838 		uint64_t pem1:1;
5839 		uint64_t pem0:1;
5840 		uint64_t ptp:1;
5841 		uint64_t agl:1;
5842 		uint64_t reserved_38_45:8;
5843 		uint64_t agx1:1;
5844 		uint64_t agx0:1;
5845 		uint64_t dpi:1;
5846 		uint64_t sli:1;
5847 		uint64_t usb:1;
5848 		uint64_t dfa:1;
5849 		uint64_t key:1;
5850 		uint64_t rad:1;
5851 		uint64_t tim:1;
5852 		uint64_t zip:1;
5853 		uint64_t pko:1;
5854 		uint64_t pip:1;
5855 		uint64_t ipd:1;
5856 		uint64_t l2c:1;
5857 		uint64_t pow:1;
5858 		uint64_t fpa:1;
5859 		uint64_t iob:1;
5860 		uint64_t mio:1;
5861 		uint64_t nand:1;
5862 		uint64_t mii1:1;
5863 		uint64_t reserved_10_17:8;
5864 		uint64_t wdog:10;
5865 #else
5866 		uint64_t wdog:10;
5867 		uint64_t reserved_10_17:8;
5868 		uint64_t mii1:1;
5869 		uint64_t nand:1;
5870 		uint64_t mio:1;
5871 		uint64_t iob:1;
5872 		uint64_t fpa:1;
5873 		uint64_t pow:1;
5874 		uint64_t l2c:1;
5875 		uint64_t ipd:1;
5876 		uint64_t pip:1;
5877 		uint64_t pko:1;
5878 		uint64_t zip:1;
5879 		uint64_t tim:1;
5880 		uint64_t rad:1;
5881 		uint64_t key:1;
5882 		uint64_t dfa:1;
5883 		uint64_t usb:1;
5884 		uint64_t sli:1;
5885 		uint64_t dpi:1;
5886 		uint64_t agx0:1;
5887 		uint64_t agx1:1;
5888 		uint64_t reserved_38_45:8;
5889 		uint64_t agl:1;
5890 		uint64_t ptp:1;
5891 		uint64_t pem0:1;
5892 		uint64_t pem1:1;
5893 		uint64_t srio0:1;
5894 		uint64_t reserved_51_51:1;
5895 		uint64_t lmc0:1;
5896 		uint64_t reserved_53_55:3;
5897 		uint64_t dfm:1;
5898 		uint64_t reserved_57_59:3;
5899 		uint64_t srio2:1;
5900 		uint64_t srio3:1;
5901 		uint64_t reserved_62_62:1;
5902 		uint64_t rst:1;
5903 #endif
5904 	} cn66xx;
5905 	struct cvmx_ciu_intx_en4_1_w1s_cnf71xx {
5906 #ifdef __BIG_ENDIAN_BITFIELD
5907 		uint64_t rst:1;
5908 		uint64_t reserved_53_62:10;
5909 		uint64_t lmc0:1;
5910 		uint64_t reserved_50_51:2;
5911 		uint64_t pem1:1;
5912 		uint64_t pem0:1;
5913 		uint64_t ptp:1;
5914 		uint64_t reserved_41_46:6;
5915 		uint64_t dpi_dma:1;
5916 		uint64_t reserved_37_39:3;
5917 		uint64_t agx0:1;
5918 		uint64_t dpi:1;
5919 		uint64_t sli:1;
5920 		uint64_t usb:1;
5921 		uint64_t reserved_32_32:1;
5922 		uint64_t key:1;
5923 		uint64_t rad:1;
5924 		uint64_t tim:1;
5925 		uint64_t reserved_28_28:1;
5926 		uint64_t pko:1;
5927 		uint64_t pip:1;
5928 		uint64_t ipd:1;
5929 		uint64_t l2c:1;
5930 		uint64_t pow:1;
5931 		uint64_t fpa:1;
5932 		uint64_t iob:1;
5933 		uint64_t mio:1;
5934 		uint64_t nand:1;
5935 		uint64_t reserved_4_18:15;
5936 		uint64_t wdog:4;
5937 #else
5938 		uint64_t wdog:4;
5939 		uint64_t reserved_4_18:15;
5940 		uint64_t nand:1;
5941 		uint64_t mio:1;
5942 		uint64_t iob:1;
5943 		uint64_t fpa:1;
5944 		uint64_t pow:1;
5945 		uint64_t l2c:1;
5946 		uint64_t ipd:1;
5947 		uint64_t pip:1;
5948 		uint64_t pko:1;
5949 		uint64_t reserved_28_28:1;
5950 		uint64_t tim:1;
5951 		uint64_t rad:1;
5952 		uint64_t key:1;
5953 		uint64_t reserved_32_32:1;
5954 		uint64_t usb:1;
5955 		uint64_t sli:1;
5956 		uint64_t dpi:1;
5957 		uint64_t agx0:1;
5958 		uint64_t reserved_37_39:3;
5959 		uint64_t dpi_dma:1;
5960 		uint64_t reserved_41_46:6;
5961 		uint64_t ptp:1;
5962 		uint64_t pem0:1;
5963 		uint64_t pem1:1;
5964 		uint64_t reserved_50_51:2;
5965 		uint64_t lmc0:1;
5966 		uint64_t reserved_53_62:10;
5967 		uint64_t rst:1;
5968 #endif
5969 	} cnf71xx;
5970 };
5971 
5972 union cvmx_ciu_intx_sum0 {
5973 	uint64_t u64;
5974 	struct cvmx_ciu_intx_sum0_s {
5975 #ifdef __BIG_ENDIAN_BITFIELD
5976 		uint64_t bootdma:1;
5977 		uint64_t mii:1;
5978 		uint64_t ipdppthr:1;
5979 		uint64_t powiq:1;
5980 		uint64_t twsi2:1;
5981 		uint64_t mpi:1;
5982 		uint64_t pcm:1;
5983 		uint64_t usb:1;
5984 		uint64_t timer:4;
5985 		uint64_t reserved_51_51:1;
5986 		uint64_t ipd_drp:1;
5987 		uint64_t gmx_drp:2;
5988 		uint64_t trace:1;
5989 		uint64_t rml:1;
5990 		uint64_t twsi:1;
5991 		uint64_t wdog_sum:1;
5992 		uint64_t pci_msi:4;
5993 		uint64_t pci_int:4;
5994 		uint64_t uart:2;
5995 		uint64_t mbox:2;
5996 		uint64_t gpio:16;
5997 		uint64_t workq:16;
5998 #else
5999 		uint64_t workq:16;
6000 		uint64_t gpio:16;
6001 		uint64_t mbox:2;
6002 		uint64_t uart:2;
6003 		uint64_t pci_int:4;
6004 		uint64_t pci_msi:4;
6005 		uint64_t wdog_sum:1;
6006 		uint64_t twsi:1;
6007 		uint64_t rml:1;
6008 		uint64_t trace:1;
6009 		uint64_t gmx_drp:2;
6010 		uint64_t ipd_drp:1;
6011 		uint64_t reserved_51_51:1;
6012 		uint64_t timer:4;
6013 		uint64_t usb:1;
6014 		uint64_t pcm:1;
6015 		uint64_t mpi:1;
6016 		uint64_t twsi2:1;
6017 		uint64_t powiq:1;
6018 		uint64_t ipdppthr:1;
6019 		uint64_t mii:1;
6020 		uint64_t bootdma:1;
6021 #endif
6022 	} s;
6023 	struct cvmx_ciu_intx_sum0_cn30xx {
6024 #ifdef __BIG_ENDIAN_BITFIELD
6025 		uint64_t reserved_59_63:5;
6026 		uint64_t mpi:1;
6027 		uint64_t pcm:1;
6028 		uint64_t usb:1;
6029 		uint64_t timer:4;
6030 		uint64_t reserved_51_51:1;
6031 		uint64_t ipd_drp:1;
6032 		uint64_t reserved_49_49:1;
6033 		uint64_t gmx_drp:1;
6034 		uint64_t reserved_47_47:1;
6035 		uint64_t rml:1;
6036 		uint64_t twsi:1;
6037 		uint64_t wdog_sum:1;
6038 		uint64_t pci_msi:4;
6039 		uint64_t pci_int:4;
6040 		uint64_t uart:2;
6041 		uint64_t mbox:2;
6042 		uint64_t gpio:16;
6043 		uint64_t workq:16;
6044 #else
6045 		uint64_t workq:16;
6046 		uint64_t gpio:16;
6047 		uint64_t mbox:2;
6048 		uint64_t uart:2;
6049 		uint64_t pci_int:4;
6050 		uint64_t pci_msi:4;
6051 		uint64_t wdog_sum:1;
6052 		uint64_t twsi:1;
6053 		uint64_t rml:1;
6054 		uint64_t reserved_47_47:1;
6055 		uint64_t gmx_drp:1;
6056 		uint64_t reserved_49_49:1;
6057 		uint64_t ipd_drp:1;
6058 		uint64_t reserved_51_51:1;
6059 		uint64_t timer:4;
6060 		uint64_t usb:1;
6061 		uint64_t pcm:1;
6062 		uint64_t mpi:1;
6063 		uint64_t reserved_59_63:5;
6064 #endif
6065 	} cn30xx;
6066 	struct cvmx_ciu_intx_sum0_cn31xx {
6067 #ifdef __BIG_ENDIAN_BITFIELD
6068 		uint64_t reserved_59_63:5;
6069 		uint64_t mpi:1;
6070 		uint64_t pcm:1;
6071 		uint64_t usb:1;
6072 		uint64_t timer:4;
6073 		uint64_t reserved_51_51:1;
6074 		uint64_t ipd_drp:1;
6075 		uint64_t reserved_49_49:1;
6076 		uint64_t gmx_drp:1;
6077 		uint64_t trace:1;
6078 		uint64_t rml:1;
6079 		uint64_t twsi:1;
6080 		uint64_t wdog_sum:1;
6081 		uint64_t pci_msi:4;
6082 		uint64_t pci_int:4;
6083 		uint64_t uart:2;
6084 		uint64_t mbox:2;
6085 		uint64_t gpio:16;
6086 		uint64_t workq:16;
6087 #else
6088 		uint64_t workq:16;
6089 		uint64_t gpio:16;
6090 		uint64_t mbox:2;
6091 		uint64_t uart:2;
6092 		uint64_t pci_int:4;
6093 		uint64_t pci_msi:4;
6094 		uint64_t wdog_sum:1;
6095 		uint64_t twsi:1;
6096 		uint64_t rml:1;
6097 		uint64_t trace:1;
6098 		uint64_t gmx_drp:1;
6099 		uint64_t reserved_49_49:1;
6100 		uint64_t ipd_drp:1;
6101 		uint64_t reserved_51_51:1;
6102 		uint64_t timer:4;
6103 		uint64_t usb:1;
6104 		uint64_t pcm:1;
6105 		uint64_t mpi:1;
6106 		uint64_t reserved_59_63:5;
6107 #endif
6108 	} cn31xx;
6109 	struct cvmx_ciu_intx_sum0_cn38xx {
6110 #ifdef __BIG_ENDIAN_BITFIELD
6111 		uint64_t reserved_56_63:8;
6112 		uint64_t timer:4;
6113 		uint64_t key_zero:1;
6114 		uint64_t ipd_drp:1;
6115 		uint64_t gmx_drp:2;
6116 		uint64_t trace:1;
6117 		uint64_t rml:1;
6118 		uint64_t twsi:1;
6119 		uint64_t wdog_sum:1;
6120 		uint64_t pci_msi:4;
6121 		uint64_t pci_int:4;
6122 		uint64_t uart:2;
6123 		uint64_t mbox:2;
6124 		uint64_t gpio:16;
6125 		uint64_t workq:16;
6126 #else
6127 		uint64_t workq:16;
6128 		uint64_t gpio:16;
6129 		uint64_t mbox:2;
6130 		uint64_t uart:2;
6131 		uint64_t pci_int:4;
6132 		uint64_t pci_msi:4;
6133 		uint64_t wdog_sum:1;
6134 		uint64_t twsi:1;
6135 		uint64_t rml:1;
6136 		uint64_t trace:1;
6137 		uint64_t gmx_drp:2;
6138 		uint64_t ipd_drp:1;
6139 		uint64_t key_zero:1;
6140 		uint64_t timer:4;
6141 		uint64_t reserved_56_63:8;
6142 #endif
6143 	} cn38xx;
6144 	struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
6145 	struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
6146 	struct cvmx_ciu_intx_sum0_cn52xx {
6147 #ifdef __BIG_ENDIAN_BITFIELD
6148 		uint64_t bootdma:1;
6149 		uint64_t mii:1;
6150 		uint64_t ipdppthr:1;
6151 		uint64_t powiq:1;
6152 		uint64_t twsi2:1;
6153 		uint64_t reserved_57_58:2;
6154 		uint64_t usb:1;
6155 		uint64_t timer:4;
6156 		uint64_t reserved_51_51:1;
6157 		uint64_t ipd_drp:1;
6158 		uint64_t reserved_49_49:1;
6159 		uint64_t gmx_drp:1;
6160 		uint64_t trace:1;
6161 		uint64_t rml:1;
6162 		uint64_t twsi:1;
6163 		uint64_t wdog_sum:1;
6164 		uint64_t pci_msi:4;
6165 		uint64_t pci_int:4;
6166 		uint64_t uart:2;
6167 		uint64_t mbox:2;
6168 		uint64_t gpio:16;
6169 		uint64_t workq:16;
6170 #else
6171 		uint64_t workq:16;
6172 		uint64_t gpio:16;
6173 		uint64_t mbox:2;
6174 		uint64_t uart:2;
6175 		uint64_t pci_int:4;
6176 		uint64_t pci_msi:4;
6177 		uint64_t wdog_sum:1;
6178 		uint64_t twsi:1;
6179 		uint64_t rml:1;
6180 		uint64_t trace:1;
6181 		uint64_t gmx_drp:1;
6182 		uint64_t reserved_49_49:1;
6183 		uint64_t ipd_drp:1;
6184 		uint64_t reserved_51_51:1;
6185 		uint64_t timer:4;
6186 		uint64_t usb:1;
6187 		uint64_t reserved_57_58:2;
6188 		uint64_t twsi2:1;
6189 		uint64_t powiq:1;
6190 		uint64_t ipdppthr:1;
6191 		uint64_t mii:1;
6192 		uint64_t bootdma:1;
6193 #endif
6194 	} cn52xx;
6195 	struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
6196 	struct cvmx_ciu_intx_sum0_cn56xx {
6197 #ifdef __BIG_ENDIAN_BITFIELD
6198 		uint64_t bootdma:1;
6199 		uint64_t mii:1;
6200 		uint64_t ipdppthr:1;
6201 		uint64_t powiq:1;
6202 		uint64_t twsi2:1;
6203 		uint64_t reserved_57_58:2;
6204 		uint64_t usb:1;
6205 		uint64_t timer:4;
6206 		uint64_t key_zero:1;
6207 		uint64_t ipd_drp:1;
6208 		uint64_t gmx_drp:2;
6209 		uint64_t trace:1;
6210 		uint64_t rml:1;
6211 		uint64_t twsi:1;
6212 		uint64_t wdog_sum:1;
6213 		uint64_t pci_msi:4;
6214 		uint64_t pci_int:4;
6215 		uint64_t uart:2;
6216 		uint64_t mbox:2;
6217 		uint64_t gpio:16;
6218 		uint64_t workq:16;
6219 #else
6220 		uint64_t workq:16;
6221 		uint64_t gpio:16;
6222 		uint64_t mbox:2;
6223 		uint64_t uart:2;
6224 		uint64_t pci_int:4;
6225 		uint64_t pci_msi:4;
6226 		uint64_t wdog_sum:1;
6227 		uint64_t twsi:1;
6228 		uint64_t rml:1;
6229 		uint64_t trace:1;
6230 		uint64_t gmx_drp:2;
6231 		uint64_t ipd_drp:1;
6232 		uint64_t key_zero:1;
6233 		uint64_t timer:4;
6234 		uint64_t usb:1;
6235 		uint64_t reserved_57_58:2;
6236 		uint64_t twsi2:1;
6237 		uint64_t powiq:1;
6238 		uint64_t ipdppthr:1;
6239 		uint64_t mii:1;
6240 		uint64_t bootdma:1;
6241 #endif
6242 	} cn56xx;
6243 	struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
6244 	struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
6245 	struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
6246 	struct cvmx_ciu_intx_sum0_cn61xx {
6247 #ifdef __BIG_ENDIAN_BITFIELD
6248 		uint64_t bootdma:1;
6249 		uint64_t mii:1;
6250 		uint64_t ipdppthr:1;
6251 		uint64_t powiq:1;
6252 		uint64_t twsi2:1;
6253 		uint64_t mpi:1;
6254 		uint64_t pcm:1;
6255 		uint64_t usb:1;
6256 		uint64_t timer:4;
6257 		uint64_t sum2:1;
6258 		uint64_t ipd_drp:1;
6259 		uint64_t gmx_drp:2;
6260 		uint64_t trace:1;
6261 		uint64_t rml:1;
6262 		uint64_t twsi:1;
6263 		uint64_t wdog_sum:1;
6264 		uint64_t pci_msi:4;
6265 		uint64_t pci_int:4;
6266 		uint64_t uart:2;
6267 		uint64_t mbox:2;
6268 		uint64_t gpio:16;
6269 		uint64_t workq:16;
6270 #else
6271 		uint64_t workq:16;
6272 		uint64_t gpio:16;
6273 		uint64_t mbox:2;
6274 		uint64_t uart:2;
6275 		uint64_t pci_int:4;
6276 		uint64_t pci_msi:4;
6277 		uint64_t wdog_sum:1;
6278 		uint64_t twsi:1;
6279 		uint64_t rml:1;
6280 		uint64_t trace:1;
6281 		uint64_t gmx_drp:2;
6282 		uint64_t ipd_drp:1;
6283 		uint64_t sum2:1;
6284 		uint64_t timer:4;
6285 		uint64_t usb:1;
6286 		uint64_t pcm:1;
6287 		uint64_t mpi:1;
6288 		uint64_t twsi2:1;
6289 		uint64_t powiq:1;
6290 		uint64_t ipdppthr:1;
6291 		uint64_t mii:1;
6292 		uint64_t bootdma:1;
6293 #endif
6294 	} cn61xx;
6295 	struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
6296 	struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
6297 	struct cvmx_ciu_intx_sum0_cn66xx {
6298 #ifdef __BIG_ENDIAN_BITFIELD
6299 		uint64_t bootdma:1;
6300 		uint64_t mii:1;
6301 		uint64_t ipdppthr:1;
6302 		uint64_t powiq:1;
6303 		uint64_t twsi2:1;
6304 		uint64_t mpi:1;
6305 		uint64_t reserved_57_57:1;
6306 		uint64_t usb:1;
6307 		uint64_t timer:4;
6308 		uint64_t sum2:1;
6309 		uint64_t ipd_drp:1;
6310 		uint64_t gmx_drp:2;
6311 		uint64_t trace:1;
6312 		uint64_t rml:1;
6313 		uint64_t twsi:1;
6314 		uint64_t wdog_sum:1;
6315 		uint64_t pci_msi:4;
6316 		uint64_t pci_int:4;
6317 		uint64_t uart:2;
6318 		uint64_t mbox:2;
6319 		uint64_t gpio:16;
6320 		uint64_t workq:16;
6321 #else
6322 		uint64_t workq:16;
6323 		uint64_t gpio:16;
6324 		uint64_t mbox:2;
6325 		uint64_t uart:2;
6326 		uint64_t pci_int:4;
6327 		uint64_t pci_msi:4;
6328 		uint64_t wdog_sum:1;
6329 		uint64_t twsi:1;
6330 		uint64_t rml:1;
6331 		uint64_t trace:1;
6332 		uint64_t gmx_drp:2;
6333 		uint64_t ipd_drp:1;
6334 		uint64_t sum2:1;
6335 		uint64_t timer:4;
6336 		uint64_t usb:1;
6337 		uint64_t reserved_57_57:1;
6338 		uint64_t mpi:1;
6339 		uint64_t twsi2:1;
6340 		uint64_t powiq:1;
6341 		uint64_t ipdppthr:1;
6342 		uint64_t mii:1;
6343 		uint64_t bootdma:1;
6344 #endif
6345 	} cn66xx;
6346 	struct cvmx_ciu_intx_sum0_cnf71xx {
6347 #ifdef __BIG_ENDIAN_BITFIELD
6348 		uint64_t bootdma:1;
6349 		uint64_t reserved_62_62:1;
6350 		uint64_t ipdppthr:1;
6351 		uint64_t powiq:1;
6352 		uint64_t twsi2:1;
6353 		uint64_t mpi:1;
6354 		uint64_t pcm:1;
6355 		uint64_t usb:1;
6356 		uint64_t timer:4;
6357 		uint64_t sum2:1;
6358 		uint64_t ipd_drp:1;
6359 		uint64_t reserved_49_49:1;
6360 		uint64_t gmx_drp:1;
6361 		uint64_t trace:1;
6362 		uint64_t rml:1;
6363 		uint64_t twsi:1;
6364 		uint64_t wdog_sum:1;
6365 		uint64_t pci_msi:4;
6366 		uint64_t pci_int:4;
6367 		uint64_t uart:2;
6368 		uint64_t mbox:2;
6369 		uint64_t gpio:16;
6370 		uint64_t workq:16;
6371 #else
6372 		uint64_t workq:16;
6373 		uint64_t gpio:16;
6374 		uint64_t mbox:2;
6375 		uint64_t uart:2;
6376 		uint64_t pci_int:4;
6377 		uint64_t pci_msi:4;
6378 		uint64_t wdog_sum:1;
6379 		uint64_t twsi:1;
6380 		uint64_t rml:1;
6381 		uint64_t trace:1;
6382 		uint64_t gmx_drp:1;
6383 		uint64_t reserved_49_49:1;
6384 		uint64_t ipd_drp:1;
6385 		uint64_t sum2:1;
6386 		uint64_t timer:4;
6387 		uint64_t usb:1;
6388 		uint64_t pcm:1;
6389 		uint64_t mpi:1;
6390 		uint64_t twsi2:1;
6391 		uint64_t powiq:1;
6392 		uint64_t ipdppthr:1;
6393 		uint64_t reserved_62_62:1;
6394 		uint64_t bootdma:1;
6395 #endif
6396 	} cnf71xx;
6397 };
6398 
6399 union cvmx_ciu_intx_sum4 {
6400 	uint64_t u64;
6401 	struct cvmx_ciu_intx_sum4_s {
6402 #ifdef __BIG_ENDIAN_BITFIELD
6403 		uint64_t bootdma:1;
6404 		uint64_t mii:1;
6405 		uint64_t ipdppthr:1;
6406 		uint64_t powiq:1;
6407 		uint64_t twsi2:1;
6408 		uint64_t mpi:1;
6409 		uint64_t pcm:1;
6410 		uint64_t usb:1;
6411 		uint64_t timer:4;
6412 		uint64_t reserved_51_51:1;
6413 		uint64_t ipd_drp:1;
6414 		uint64_t gmx_drp:2;
6415 		uint64_t trace:1;
6416 		uint64_t rml:1;
6417 		uint64_t twsi:1;
6418 		uint64_t wdog_sum:1;
6419 		uint64_t pci_msi:4;
6420 		uint64_t pci_int:4;
6421 		uint64_t uart:2;
6422 		uint64_t mbox:2;
6423 		uint64_t gpio:16;
6424 		uint64_t workq:16;
6425 #else
6426 		uint64_t workq:16;
6427 		uint64_t gpio:16;
6428 		uint64_t mbox:2;
6429 		uint64_t uart:2;
6430 		uint64_t pci_int:4;
6431 		uint64_t pci_msi:4;
6432 		uint64_t wdog_sum:1;
6433 		uint64_t twsi:1;
6434 		uint64_t rml:1;
6435 		uint64_t trace:1;
6436 		uint64_t gmx_drp:2;
6437 		uint64_t ipd_drp:1;
6438 		uint64_t reserved_51_51:1;
6439 		uint64_t timer:4;
6440 		uint64_t usb:1;
6441 		uint64_t pcm:1;
6442 		uint64_t mpi:1;
6443 		uint64_t twsi2:1;
6444 		uint64_t powiq:1;
6445 		uint64_t ipdppthr:1;
6446 		uint64_t mii:1;
6447 		uint64_t bootdma:1;
6448 #endif
6449 	} s;
6450 	struct cvmx_ciu_intx_sum4_cn50xx {
6451 #ifdef __BIG_ENDIAN_BITFIELD
6452 		uint64_t reserved_59_63:5;
6453 		uint64_t mpi:1;
6454 		uint64_t pcm:1;
6455 		uint64_t usb:1;
6456 		uint64_t timer:4;
6457 		uint64_t reserved_51_51:1;
6458 		uint64_t ipd_drp:1;
6459 		uint64_t reserved_49_49:1;
6460 		uint64_t gmx_drp:1;
6461 		uint64_t reserved_47_47:1;
6462 		uint64_t rml:1;
6463 		uint64_t twsi:1;
6464 		uint64_t wdog_sum:1;
6465 		uint64_t pci_msi:4;
6466 		uint64_t pci_int:4;
6467 		uint64_t uart:2;
6468 		uint64_t mbox:2;
6469 		uint64_t gpio:16;
6470 		uint64_t workq:16;
6471 #else
6472 		uint64_t workq:16;
6473 		uint64_t gpio:16;
6474 		uint64_t mbox:2;
6475 		uint64_t uart:2;
6476 		uint64_t pci_int:4;
6477 		uint64_t pci_msi:4;
6478 		uint64_t wdog_sum:1;
6479 		uint64_t twsi:1;
6480 		uint64_t rml:1;
6481 		uint64_t reserved_47_47:1;
6482 		uint64_t gmx_drp:1;
6483 		uint64_t reserved_49_49:1;
6484 		uint64_t ipd_drp:1;
6485 		uint64_t reserved_51_51:1;
6486 		uint64_t timer:4;
6487 		uint64_t usb:1;
6488 		uint64_t pcm:1;
6489 		uint64_t mpi:1;
6490 		uint64_t reserved_59_63:5;
6491 #endif
6492 	} cn50xx;
6493 	struct cvmx_ciu_intx_sum4_cn52xx {
6494 #ifdef __BIG_ENDIAN_BITFIELD
6495 		uint64_t bootdma:1;
6496 		uint64_t mii:1;
6497 		uint64_t ipdppthr:1;
6498 		uint64_t powiq:1;
6499 		uint64_t twsi2:1;
6500 		uint64_t reserved_57_58:2;
6501 		uint64_t usb:1;
6502 		uint64_t timer:4;
6503 		uint64_t reserved_51_51:1;
6504 		uint64_t ipd_drp:1;
6505 		uint64_t reserved_49_49:1;
6506 		uint64_t gmx_drp:1;
6507 		uint64_t trace:1;
6508 		uint64_t rml:1;
6509 		uint64_t twsi:1;
6510 		uint64_t wdog_sum:1;
6511 		uint64_t pci_msi:4;
6512 		uint64_t pci_int:4;
6513 		uint64_t uart:2;
6514 		uint64_t mbox:2;
6515 		uint64_t gpio:16;
6516 		uint64_t workq:16;
6517 #else
6518 		uint64_t workq:16;
6519 		uint64_t gpio:16;
6520 		uint64_t mbox:2;
6521 		uint64_t uart:2;
6522 		uint64_t pci_int:4;
6523 		uint64_t pci_msi:4;
6524 		uint64_t wdog_sum:1;
6525 		uint64_t twsi:1;
6526 		uint64_t rml:1;
6527 		uint64_t trace:1;
6528 		uint64_t gmx_drp:1;
6529 		uint64_t reserved_49_49:1;
6530 		uint64_t ipd_drp:1;
6531 		uint64_t reserved_51_51:1;
6532 		uint64_t timer:4;
6533 		uint64_t usb:1;
6534 		uint64_t reserved_57_58:2;
6535 		uint64_t twsi2:1;
6536 		uint64_t powiq:1;
6537 		uint64_t ipdppthr:1;
6538 		uint64_t mii:1;
6539 		uint64_t bootdma:1;
6540 #endif
6541 	} cn52xx;
6542 	struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
6543 	struct cvmx_ciu_intx_sum4_cn56xx {
6544 #ifdef __BIG_ENDIAN_BITFIELD
6545 		uint64_t bootdma:1;
6546 		uint64_t mii:1;
6547 		uint64_t ipdppthr:1;
6548 		uint64_t powiq:1;
6549 		uint64_t twsi2:1;
6550 		uint64_t reserved_57_58:2;
6551 		uint64_t usb:1;
6552 		uint64_t timer:4;
6553 		uint64_t key_zero:1;
6554 		uint64_t ipd_drp:1;
6555 		uint64_t gmx_drp:2;
6556 		uint64_t trace:1;
6557 		uint64_t rml:1;
6558 		uint64_t twsi:1;
6559 		uint64_t wdog_sum:1;
6560 		uint64_t pci_msi:4;
6561 		uint64_t pci_int:4;
6562 		uint64_t uart:2;
6563 		uint64_t mbox:2;
6564 		uint64_t gpio:16;
6565 		uint64_t workq:16;
6566 #else
6567 		uint64_t workq:16;
6568 		uint64_t gpio:16;
6569 		uint64_t mbox:2;
6570 		uint64_t uart:2;
6571 		uint64_t pci_int:4;
6572 		uint64_t pci_msi:4;
6573 		uint64_t wdog_sum:1;
6574 		uint64_t twsi:1;
6575 		uint64_t rml:1;
6576 		uint64_t trace:1;
6577 		uint64_t gmx_drp:2;
6578 		uint64_t ipd_drp:1;
6579 		uint64_t key_zero:1;
6580 		uint64_t timer:4;
6581 		uint64_t usb:1;
6582 		uint64_t reserved_57_58:2;
6583 		uint64_t twsi2:1;
6584 		uint64_t powiq:1;
6585 		uint64_t ipdppthr:1;
6586 		uint64_t mii:1;
6587 		uint64_t bootdma:1;
6588 #endif
6589 	} cn56xx;
6590 	struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
6591 	struct cvmx_ciu_intx_sum4_cn58xx {
6592 #ifdef __BIG_ENDIAN_BITFIELD
6593 		uint64_t reserved_56_63:8;
6594 		uint64_t timer:4;
6595 		uint64_t key_zero:1;
6596 		uint64_t ipd_drp:1;
6597 		uint64_t gmx_drp:2;
6598 		uint64_t trace:1;
6599 		uint64_t rml:1;
6600 		uint64_t twsi:1;
6601 		uint64_t wdog_sum:1;
6602 		uint64_t pci_msi:4;
6603 		uint64_t pci_int:4;
6604 		uint64_t uart:2;
6605 		uint64_t mbox:2;
6606 		uint64_t gpio:16;
6607 		uint64_t workq:16;
6608 #else
6609 		uint64_t workq:16;
6610 		uint64_t gpio:16;
6611 		uint64_t mbox:2;
6612 		uint64_t uart:2;
6613 		uint64_t pci_int:4;
6614 		uint64_t pci_msi:4;
6615 		uint64_t wdog_sum:1;
6616 		uint64_t twsi:1;
6617 		uint64_t rml:1;
6618 		uint64_t trace:1;
6619 		uint64_t gmx_drp:2;
6620 		uint64_t ipd_drp:1;
6621 		uint64_t key_zero:1;
6622 		uint64_t timer:4;
6623 		uint64_t reserved_56_63:8;
6624 #endif
6625 	} cn58xx;
6626 	struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
6627 	struct cvmx_ciu_intx_sum4_cn61xx {
6628 #ifdef __BIG_ENDIAN_BITFIELD
6629 		uint64_t bootdma:1;
6630 		uint64_t mii:1;
6631 		uint64_t ipdppthr:1;
6632 		uint64_t powiq:1;
6633 		uint64_t twsi2:1;
6634 		uint64_t mpi:1;
6635 		uint64_t pcm:1;
6636 		uint64_t usb:1;
6637 		uint64_t timer:4;
6638 		uint64_t sum2:1;
6639 		uint64_t ipd_drp:1;
6640 		uint64_t gmx_drp:2;
6641 		uint64_t trace:1;
6642 		uint64_t rml:1;
6643 		uint64_t twsi:1;
6644 		uint64_t wdog_sum:1;
6645 		uint64_t pci_msi:4;
6646 		uint64_t pci_int:4;
6647 		uint64_t uart:2;
6648 		uint64_t mbox:2;
6649 		uint64_t gpio:16;
6650 		uint64_t workq:16;
6651 #else
6652 		uint64_t workq:16;
6653 		uint64_t gpio:16;
6654 		uint64_t mbox:2;
6655 		uint64_t uart:2;
6656 		uint64_t pci_int:4;
6657 		uint64_t pci_msi:4;
6658 		uint64_t wdog_sum:1;
6659 		uint64_t twsi:1;
6660 		uint64_t rml:1;
6661 		uint64_t trace:1;
6662 		uint64_t gmx_drp:2;
6663 		uint64_t ipd_drp:1;
6664 		uint64_t sum2:1;
6665 		uint64_t timer:4;
6666 		uint64_t usb:1;
6667 		uint64_t pcm:1;
6668 		uint64_t mpi:1;
6669 		uint64_t twsi2:1;
6670 		uint64_t powiq:1;
6671 		uint64_t ipdppthr:1;
6672 		uint64_t mii:1;
6673 		uint64_t bootdma:1;
6674 #endif
6675 	} cn61xx;
6676 	struct cvmx_ciu_intx_sum4_cn52xx cn63xx;
6677 	struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1;
6678 	struct cvmx_ciu_intx_sum4_cn66xx {
6679 #ifdef __BIG_ENDIAN_BITFIELD
6680 		uint64_t bootdma:1;
6681 		uint64_t mii:1;
6682 		uint64_t ipdppthr:1;
6683 		uint64_t powiq:1;
6684 		uint64_t twsi2:1;
6685 		uint64_t mpi:1;
6686 		uint64_t reserved_57_57:1;
6687 		uint64_t usb:1;
6688 		uint64_t timer:4;
6689 		uint64_t sum2:1;
6690 		uint64_t ipd_drp:1;
6691 		uint64_t gmx_drp:2;
6692 		uint64_t trace:1;
6693 		uint64_t rml:1;
6694 		uint64_t twsi:1;
6695 		uint64_t wdog_sum:1;
6696 		uint64_t pci_msi:4;
6697 		uint64_t pci_int:4;
6698 		uint64_t uart:2;
6699 		uint64_t mbox:2;
6700 		uint64_t gpio:16;
6701 		uint64_t workq:16;
6702 #else
6703 		uint64_t workq:16;
6704 		uint64_t gpio:16;
6705 		uint64_t mbox:2;
6706 		uint64_t uart:2;
6707 		uint64_t pci_int:4;
6708 		uint64_t pci_msi:4;
6709 		uint64_t wdog_sum:1;
6710 		uint64_t twsi:1;
6711 		uint64_t rml:1;
6712 		uint64_t trace:1;
6713 		uint64_t gmx_drp:2;
6714 		uint64_t ipd_drp:1;
6715 		uint64_t sum2:1;
6716 		uint64_t timer:4;
6717 		uint64_t usb:1;
6718 		uint64_t reserved_57_57:1;
6719 		uint64_t mpi:1;
6720 		uint64_t twsi2:1;
6721 		uint64_t powiq:1;
6722 		uint64_t ipdppthr:1;
6723 		uint64_t mii:1;
6724 		uint64_t bootdma:1;
6725 #endif
6726 	} cn66xx;
6727 	struct cvmx_ciu_intx_sum4_cnf71xx {
6728 #ifdef __BIG_ENDIAN_BITFIELD
6729 		uint64_t bootdma:1;
6730 		uint64_t reserved_62_62:1;
6731 		uint64_t ipdppthr:1;
6732 		uint64_t powiq:1;
6733 		uint64_t twsi2:1;
6734 		uint64_t mpi:1;
6735 		uint64_t pcm:1;
6736 		uint64_t usb:1;
6737 		uint64_t timer:4;
6738 		uint64_t sum2:1;
6739 		uint64_t ipd_drp:1;
6740 		uint64_t reserved_49_49:1;
6741 		uint64_t gmx_drp:1;
6742 		uint64_t trace:1;
6743 		uint64_t rml:1;
6744 		uint64_t twsi:1;
6745 		uint64_t wdog_sum:1;
6746 		uint64_t pci_msi:4;
6747 		uint64_t pci_int:4;
6748 		uint64_t uart:2;
6749 		uint64_t mbox:2;
6750 		uint64_t gpio:16;
6751 		uint64_t workq:16;
6752 #else
6753 		uint64_t workq:16;
6754 		uint64_t gpio:16;
6755 		uint64_t mbox:2;
6756 		uint64_t uart:2;
6757 		uint64_t pci_int:4;
6758 		uint64_t pci_msi:4;
6759 		uint64_t wdog_sum:1;
6760 		uint64_t twsi:1;
6761 		uint64_t rml:1;
6762 		uint64_t trace:1;
6763 		uint64_t gmx_drp:1;
6764 		uint64_t reserved_49_49:1;
6765 		uint64_t ipd_drp:1;
6766 		uint64_t sum2:1;
6767 		uint64_t timer:4;
6768 		uint64_t usb:1;
6769 		uint64_t pcm:1;
6770 		uint64_t mpi:1;
6771 		uint64_t twsi2:1;
6772 		uint64_t powiq:1;
6773 		uint64_t ipdppthr:1;
6774 		uint64_t reserved_62_62:1;
6775 		uint64_t bootdma:1;
6776 #endif
6777 	} cnf71xx;
6778 };
6779 
6780 union cvmx_ciu_int33_sum0 {
6781 	uint64_t u64;
6782 	struct cvmx_ciu_int33_sum0_s {
6783 #ifdef __BIG_ENDIAN_BITFIELD
6784 		uint64_t bootdma:1;
6785 		uint64_t mii:1;
6786 		uint64_t ipdppthr:1;
6787 		uint64_t powiq:1;
6788 		uint64_t twsi2:1;
6789 		uint64_t mpi:1;
6790 		uint64_t pcm:1;
6791 		uint64_t usb:1;
6792 		uint64_t timer:4;
6793 		uint64_t sum2:1;
6794 		uint64_t ipd_drp:1;
6795 		uint64_t gmx_drp:2;
6796 		uint64_t trace:1;
6797 		uint64_t rml:1;
6798 		uint64_t twsi:1;
6799 		uint64_t wdog_sum:1;
6800 		uint64_t pci_msi:4;
6801 		uint64_t pci_int:4;
6802 		uint64_t uart:2;
6803 		uint64_t mbox:2;
6804 		uint64_t gpio:16;
6805 		uint64_t workq:16;
6806 #else
6807 		uint64_t workq:16;
6808 		uint64_t gpio:16;
6809 		uint64_t mbox:2;
6810 		uint64_t uart:2;
6811 		uint64_t pci_int:4;
6812 		uint64_t pci_msi:4;
6813 		uint64_t wdog_sum:1;
6814 		uint64_t twsi:1;
6815 		uint64_t rml:1;
6816 		uint64_t trace:1;
6817 		uint64_t gmx_drp:2;
6818 		uint64_t ipd_drp:1;
6819 		uint64_t sum2:1;
6820 		uint64_t timer:4;
6821 		uint64_t usb:1;
6822 		uint64_t pcm:1;
6823 		uint64_t mpi:1;
6824 		uint64_t twsi2:1;
6825 		uint64_t powiq:1;
6826 		uint64_t ipdppthr:1;
6827 		uint64_t mii:1;
6828 		uint64_t bootdma:1;
6829 #endif
6830 	} s;
6831 	struct cvmx_ciu_int33_sum0_s cn61xx;
6832 	struct cvmx_ciu_int33_sum0_cn63xx {
6833 #ifdef __BIG_ENDIAN_BITFIELD
6834 		uint64_t bootdma:1;
6835 		uint64_t mii:1;
6836 		uint64_t ipdppthr:1;
6837 		uint64_t powiq:1;
6838 		uint64_t twsi2:1;
6839 		uint64_t reserved_57_58:2;
6840 		uint64_t usb:1;
6841 		uint64_t timer:4;
6842 		uint64_t reserved_51_51:1;
6843 		uint64_t ipd_drp:1;
6844 		uint64_t reserved_49_49:1;
6845 		uint64_t gmx_drp:1;
6846 		uint64_t trace:1;
6847 		uint64_t rml:1;
6848 		uint64_t twsi:1;
6849 		uint64_t wdog_sum:1;
6850 		uint64_t pci_msi:4;
6851 		uint64_t pci_int:4;
6852 		uint64_t uart:2;
6853 		uint64_t mbox:2;
6854 		uint64_t gpio:16;
6855 		uint64_t workq:16;
6856 #else
6857 		uint64_t workq:16;
6858 		uint64_t gpio:16;
6859 		uint64_t mbox:2;
6860 		uint64_t uart:2;
6861 		uint64_t pci_int:4;
6862 		uint64_t pci_msi:4;
6863 		uint64_t wdog_sum:1;
6864 		uint64_t twsi:1;
6865 		uint64_t rml:1;
6866 		uint64_t trace:1;
6867 		uint64_t gmx_drp:1;
6868 		uint64_t reserved_49_49:1;
6869 		uint64_t ipd_drp:1;
6870 		uint64_t reserved_51_51:1;
6871 		uint64_t timer:4;
6872 		uint64_t usb:1;
6873 		uint64_t reserved_57_58:2;
6874 		uint64_t twsi2:1;
6875 		uint64_t powiq:1;
6876 		uint64_t ipdppthr:1;
6877 		uint64_t mii:1;
6878 		uint64_t bootdma:1;
6879 #endif
6880 	} cn63xx;
6881 	struct cvmx_ciu_int33_sum0_cn63xx cn63xxp1;
6882 	struct cvmx_ciu_int33_sum0_cn66xx {
6883 #ifdef __BIG_ENDIAN_BITFIELD
6884 		uint64_t bootdma:1;
6885 		uint64_t mii:1;
6886 		uint64_t ipdppthr:1;
6887 		uint64_t powiq:1;
6888 		uint64_t twsi2:1;
6889 		uint64_t mpi:1;
6890 		uint64_t reserved_57_57:1;
6891 		uint64_t usb:1;
6892 		uint64_t timer:4;
6893 		uint64_t sum2:1;
6894 		uint64_t ipd_drp:1;
6895 		uint64_t gmx_drp:2;
6896 		uint64_t trace:1;
6897 		uint64_t rml:1;
6898 		uint64_t twsi:1;
6899 		uint64_t wdog_sum:1;
6900 		uint64_t pci_msi:4;
6901 		uint64_t pci_int:4;
6902 		uint64_t uart:2;
6903 		uint64_t mbox:2;
6904 		uint64_t gpio:16;
6905 		uint64_t workq:16;
6906 #else
6907 		uint64_t workq:16;
6908 		uint64_t gpio:16;
6909 		uint64_t mbox:2;
6910 		uint64_t uart:2;
6911 		uint64_t pci_int:4;
6912 		uint64_t pci_msi:4;
6913 		uint64_t wdog_sum:1;
6914 		uint64_t twsi:1;
6915 		uint64_t rml:1;
6916 		uint64_t trace:1;
6917 		uint64_t gmx_drp:2;
6918 		uint64_t ipd_drp:1;
6919 		uint64_t sum2:1;
6920 		uint64_t timer:4;
6921 		uint64_t usb:1;
6922 		uint64_t reserved_57_57:1;
6923 		uint64_t mpi:1;
6924 		uint64_t twsi2:1;
6925 		uint64_t powiq:1;
6926 		uint64_t ipdppthr:1;
6927 		uint64_t mii:1;
6928 		uint64_t bootdma:1;
6929 #endif
6930 	} cn66xx;
6931 	struct cvmx_ciu_int33_sum0_cnf71xx {
6932 #ifdef __BIG_ENDIAN_BITFIELD
6933 		uint64_t bootdma:1;
6934 		uint64_t reserved_62_62:1;
6935 		uint64_t ipdppthr:1;
6936 		uint64_t powiq:1;
6937 		uint64_t twsi2:1;
6938 		uint64_t mpi:1;
6939 		uint64_t pcm:1;
6940 		uint64_t usb:1;
6941 		uint64_t timer:4;
6942 		uint64_t sum2:1;
6943 		uint64_t ipd_drp:1;
6944 		uint64_t reserved_49_49:1;
6945 		uint64_t gmx_drp:1;
6946 		uint64_t trace:1;
6947 		uint64_t rml:1;
6948 		uint64_t twsi:1;
6949 		uint64_t wdog_sum:1;
6950 		uint64_t pci_msi:4;
6951 		uint64_t pci_int:4;
6952 		uint64_t uart:2;
6953 		uint64_t mbox:2;
6954 		uint64_t gpio:16;
6955 		uint64_t workq:16;
6956 #else
6957 		uint64_t workq:16;
6958 		uint64_t gpio:16;
6959 		uint64_t mbox:2;
6960 		uint64_t uart:2;
6961 		uint64_t pci_int:4;
6962 		uint64_t pci_msi:4;
6963 		uint64_t wdog_sum:1;
6964 		uint64_t twsi:1;
6965 		uint64_t rml:1;
6966 		uint64_t trace:1;
6967 		uint64_t gmx_drp:1;
6968 		uint64_t reserved_49_49:1;
6969 		uint64_t ipd_drp:1;
6970 		uint64_t sum2:1;
6971 		uint64_t timer:4;
6972 		uint64_t usb:1;
6973 		uint64_t pcm:1;
6974 		uint64_t mpi:1;
6975 		uint64_t twsi2:1;
6976 		uint64_t powiq:1;
6977 		uint64_t ipdppthr:1;
6978 		uint64_t reserved_62_62:1;
6979 		uint64_t bootdma:1;
6980 #endif
6981 	} cnf71xx;
6982 };
6983 
6984 union cvmx_ciu_int_dbg_sel {
6985 	uint64_t u64;
6986 	struct cvmx_ciu_int_dbg_sel_s {
6987 #ifdef __BIG_ENDIAN_BITFIELD
6988 		uint64_t reserved_19_63:45;
6989 		uint64_t sel:3;
6990 		uint64_t reserved_10_15:6;
6991 		uint64_t irq:2;
6992 		uint64_t reserved_5_7:3;
6993 		uint64_t pp:5;
6994 #else
6995 		uint64_t pp:5;
6996 		uint64_t reserved_5_7:3;
6997 		uint64_t irq:2;
6998 		uint64_t reserved_10_15:6;
6999 		uint64_t sel:3;
7000 		uint64_t reserved_19_63:45;
7001 #endif
7002 	} s;
7003 	struct cvmx_ciu_int_dbg_sel_cn61xx {
7004 #ifdef __BIG_ENDIAN_BITFIELD
7005 		uint64_t reserved_19_63:45;
7006 		uint64_t sel:3;
7007 		uint64_t reserved_10_15:6;
7008 		uint64_t irq:2;
7009 		uint64_t reserved_4_7:4;
7010 		uint64_t pp:4;
7011 #else
7012 		uint64_t pp:4;
7013 		uint64_t reserved_4_7:4;
7014 		uint64_t irq:2;
7015 		uint64_t reserved_10_15:6;
7016 		uint64_t sel:3;
7017 		uint64_t reserved_19_63:45;
7018 #endif
7019 	} cn61xx;
7020 	struct cvmx_ciu_int_dbg_sel_cn63xx {
7021 #ifdef __BIG_ENDIAN_BITFIELD
7022 		uint64_t reserved_19_63:45;
7023 		uint64_t sel:3;
7024 		uint64_t reserved_10_15:6;
7025 		uint64_t irq:2;
7026 		uint64_t reserved_3_7:5;
7027 		uint64_t pp:3;
7028 #else
7029 		uint64_t pp:3;
7030 		uint64_t reserved_3_7:5;
7031 		uint64_t irq:2;
7032 		uint64_t reserved_10_15:6;
7033 		uint64_t sel:3;
7034 		uint64_t reserved_19_63:45;
7035 #endif
7036 	} cn63xx;
7037 	struct cvmx_ciu_int_dbg_sel_cn61xx cn66xx;
7038 	struct cvmx_ciu_int_dbg_sel_s cn68xx;
7039 	struct cvmx_ciu_int_dbg_sel_s cn68xxp1;
7040 	struct cvmx_ciu_int_dbg_sel_cn61xx cnf71xx;
7041 };
7042 
7043 union cvmx_ciu_int_sum1 {
7044 	uint64_t u64;
7045 	struct cvmx_ciu_int_sum1_s {
7046 #ifdef __BIG_ENDIAN_BITFIELD
7047 		uint64_t rst:1;
7048 		uint64_t reserved_62_62:1;
7049 		uint64_t srio3:1;
7050 		uint64_t srio2:1;
7051 		uint64_t reserved_57_59:3;
7052 		uint64_t dfm:1;
7053 		uint64_t reserved_53_55:3;
7054 		uint64_t lmc0:1;
7055 		uint64_t srio1:1;
7056 		uint64_t srio0:1;
7057 		uint64_t pem1:1;
7058 		uint64_t pem0:1;
7059 		uint64_t ptp:1;
7060 		uint64_t agl:1;
7061 		uint64_t reserved_38_45:8;
7062 		uint64_t agx1:1;
7063 		uint64_t agx0:1;
7064 		uint64_t dpi:1;
7065 		uint64_t sli:1;
7066 		uint64_t usb:1;
7067 		uint64_t dfa:1;
7068 		uint64_t key:1;
7069 		uint64_t rad:1;
7070 		uint64_t tim:1;
7071 		uint64_t zip:1;
7072 		uint64_t pko:1;
7073 		uint64_t pip:1;
7074 		uint64_t ipd:1;
7075 		uint64_t l2c:1;
7076 		uint64_t pow:1;
7077 		uint64_t fpa:1;
7078 		uint64_t iob:1;
7079 		uint64_t mio:1;
7080 		uint64_t nand:1;
7081 		uint64_t mii1:1;
7082 		uint64_t usb1:1;
7083 		uint64_t uart2:1;
7084 		uint64_t wdog:16;
7085 #else
7086 		uint64_t wdog:16;
7087 		uint64_t uart2:1;
7088 		uint64_t usb1:1;
7089 		uint64_t mii1:1;
7090 		uint64_t nand:1;
7091 		uint64_t mio:1;
7092 		uint64_t iob:1;
7093 		uint64_t fpa:1;
7094 		uint64_t pow:1;
7095 		uint64_t l2c:1;
7096 		uint64_t ipd:1;
7097 		uint64_t pip:1;
7098 		uint64_t pko:1;
7099 		uint64_t zip:1;
7100 		uint64_t tim:1;
7101 		uint64_t rad:1;
7102 		uint64_t key:1;
7103 		uint64_t dfa:1;
7104 		uint64_t usb:1;
7105 		uint64_t sli:1;
7106 		uint64_t dpi:1;
7107 		uint64_t agx0:1;
7108 		uint64_t agx1:1;
7109 		uint64_t reserved_38_45:8;
7110 		uint64_t agl:1;
7111 		uint64_t ptp:1;
7112 		uint64_t pem0:1;
7113 		uint64_t pem1:1;
7114 		uint64_t srio0:1;
7115 		uint64_t srio1:1;
7116 		uint64_t lmc0:1;
7117 		uint64_t reserved_53_55:3;
7118 		uint64_t dfm:1;
7119 		uint64_t reserved_57_59:3;
7120 		uint64_t srio2:1;
7121 		uint64_t srio3:1;
7122 		uint64_t reserved_62_62:1;
7123 		uint64_t rst:1;
7124 #endif
7125 	} s;
7126 	struct cvmx_ciu_int_sum1_cn30xx {
7127 #ifdef __BIG_ENDIAN_BITFIELD
7128 		uint64_t reserved_1_63:63;
7129 		uint64_t wdog:1;
7130 #else
7131 		uint64_t wdog:1;
7132 		uint64_t reserved_1_63:63;
7133 #endif
7134 	} cn30xx;
7135 	struct cvmx_ciu_int_sum1_cn31xx {
7136 #ifdef __BIG_ENDIAN_BITFIELD
7137 		uint64_t reserved_2_63:62;
7138 		uint64_t wdog:2;
7139 #else
7140 		uint64_t wdog:2;
7141 		uint64_t reserved_2_63:62;
7142 #endif
7143 	} cn31xx;
7144 	struct cvmx_ciu_int_sum1_cn38xx {
7145 #ifdef __BIG_ENDIAN_BITFIELD
7146 		uint64_t reserved_16_63:48;
7147 		uint64_t wdog:16;
7148 #else
7149 		uint64_t wdog:16;
7150 		uint64_t reserved_16_63:48;
7151 #endif
7152 	} cn38xx;
7153 	struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
7154 	struct cvmx_ciu_int_sum1_cn31xx cn50xx;
7155 	struct cvmx_ciu_int_sum1_cn52xx {
7156 #ifdef __BIG_ENDIAN_BITFIELD
7157 		uint64_t reserved_20_63:44;
7158 		uint64_t nand:1;
7159 		uint64_t mii1:1;
7160 		uint64_t usb1:1;
7161 		uint64_t uart2:1;
7162 		uint64_t reserved_4_15:12;
7163 		uint64_t wdog:4;
7164 #else
7165 		uint64_t wdog:4;
7166 		uint64_t reserved_4_15:12;
7167 		uint64_t uart2:1;
7168 		uint64_t usb1:1;
7169 		uint64_t mii1:1;
7170 		uint64_t nand:1;
7171 		uint64_t reserved_20_63:44;
7172 #endif
7173 	} cn52xx;
7174 	struct cvmx_ciu_int_sum1_cn52xxp1 {
7175 #ifdef __BIG_ENDIAN_BITFIELD
7176 		uint64_t reserved_19_63:45;
7177 		uint64_t mii1:1;
7178 		uint64_t usb1:1;
7179 		uint64_t uart2:1;
7180 		uint64_t reserved_4_15:12;
7181 		uint64_t wdog:4;
7182 #else
7183 		uint64_t wdog:4;
7184 		uint64_t reserved_4_15:12;
7185 		uint64_t uart2:1;
7186 		uint64_t usb1:1;
7187 		uint64_t mii1:1;
7188 		uint64_t reserved_19_63:45;
7189 #endif
7190 	} cn52xxp1;
7191 	struct cvmx_ciu_int_sum1_cn56xx {
7192 #ifdef __BIG_ENDIAN_BITFIELD
7193 		uint64_t reserved_12_63:52;
7194 		uint64_t wdog:12;
7195 #else
7196 		uint64_t wdog:12;
7197 		uint64_t reserved_12_63:52;
7198 #endif
7199 	} cn56xx;
7200 	struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
7201 	struct cvmx_ciu_int_sum1_cn38xx cn58xx;
7202 	struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
7203 	struct cvmx_ciu_int_sum1_cn61xx {
7204 #ifdef __BIG_ENDIAN_BITFIELD
7205 		uint64_t rst:1;
7206 		uint64_t reserved_53_62:10;
7207 		uint64_t lmc0:1;
7208 		uint64_t reserved_50_51:2;
7209 		uint64_t pem1:1;
7210 		uint64_t pem0:1;
7211 		uint64_t ptp:1;
7212 		uint64_t agl:1;
7213 		uint64_t reserved_38_45:8;
7214 		uint64_t agx1:1;
7215 		uint64_t agx0:1;
7216 		uint64_t dpi:1;
7217 		uint64_t sli:1;
7218 		uint64_t usb:1;
7219 		uint64_t dfa:1;
7220 		uint64_t key:1;
7221 		uint64_t rad:1;
7222 		uint64_t tim:1;
7223 		uint64_t zip:1;
7224 		uint64_t pko:1;
7225 		uint64_t pip:1;
7226 		uint64_t ipd:1;
7227 		uint64_t l2c:1;
7228 		uint64_t pow:1;
7229 		uint64_t fpa:1;
7230 		uint64_t iob:1;
7231 		uint64_t mio:1;
7232 		uint64_t nand:1;
7233 		uint64_t mii1:1;
7234 		uint64_t reserved_4_17:14;
7235 		uint64_t wdog:4;
7236 #else
7237 		uint64_t wdog:4;
7238 		uint64_t reserved_4_17:14;
7239 		uint64_t mii1:1;
7240 		uint64_t nand:1;
7241 		uint64_t mio:1;
7242 		uint64_t iob:1;
7243 		uint64_t fpa:1;
7244 		uint64_t pow:1;
7245 		uint64_t l2c:1;
7246 		uint64_t ipd:1;
7247 		uint64_t pip:1;
7248 		uint64_t pko:1;
7249 		uint64_t zip:1;
7250 		uint64_t tim:1;
7251 		uint64_t rad:1;
7252 		uint64_t key:1;
7253 		uint64_t dfa:1;
7254 		uint64_t usb:1;
7255 		uint64_t sli:1;
7256 		uint64_t dpi:1;
7257 		uint64_t agx0:1;
7258 		uint64_t agx1:1;
7259 		uint64_t reserved_38_45:8;
7260 		uint64_t agl:1;
7261 		uint64_t ptp:1;
7262 		uint64_t pem0:1;
7263 		uint64_t pem1:1;
7264 		uint64_t reserved_50_51:2;
7265 		uint64_t lmc0:1;
7266 		uint64_t reserved_53_62:10;
7267 		uint64_t rst:1;
7268 #endif
7269 	} cn61xx;
7270 	struct cvmx_ciu_int_sum1_cn63xx {
7271 #ifdef __BIG_ENDIAN_BITFIELD
7272 		uint64_t rst:1;
7273 		uint64_t reserved_57_62:6;
7274 		uint64_t dfm:1;
7275 		uint64_t reserved_53_55:3;
7276 		uint64_t lmc0:1;
7277 		uint64_t srio1:1;
7278 		uint64_t srio0:1;
7279 		uint64_t pem1:1;
7280 		uint64_t pem0:1;
7281 		uint64_t ptp:1;
7282 		uint64_t agl:1;
7283 		uint64_t reserved_37_45:9;
7284 		uint64_t agx0:1;
7285 		uint64_t dpi:1;
7286 		uint64_t sli:1;
7287 		uint64_t usb:1;
7288 		uint64_t dfa:1;
7289 		uint64_t key:1;
7290 		uint64_t rad:1;
7291 		uint64_t tim:1;
7292 		uint64_t zip:1;
7293 		uint64_t pko:1;
7294 		uint64_t pip:1;
7295 		uint64_t ipd:1;
7296 		uint64_t l2c:1;
7297 		uint64_t pow:1;
7298 		uint64_t fpa:1;
7299 		uint64_t iob:1;
7300 		uint64_t mio:1;
7301 		uint64_t nand:1;
7302 		uint64_t mii1:1;
7303 		uint64_t reserved_6_17:12;
7304 		uint64_t wdog:6;
7305 #else
7306 		uint64_t wdog:6;
7307 		uint64_t reserved_6_17:12;
7308 		uint64_t mii1:1;
7309 		uint64_t nand:1;
7310 		uint64_t mio:1;
7311 		uint64_t iob:1;
7312 		uint64_t fpa:1;
7313 		uint64_t pow:1;
7314 		uint64_t l2c:1;
7315 		uint64_t ipd:1;
7316 		uint64_t pip:1;
7317 		uint64_t pko:1;
7318 		uint64_t zip:1;
7319 		uint64_t tim:1;
7320 		uint64_t rad:1;
7321 		uint64_t key:1;
7322 		uint64_t dfa:1;
7323 		uint64_t usb:1;
7324 		uint64_t sli:1;
7325 		uint64_t dpi:1;
7326 		uint64_t agx0:1;
7327 		uint64_t reserved_37_45:9;
7328 		uint64_t agl:1;
7329 		uint64_t ptp:1;
7330 		uint64_t pem0:1;
7331 		uint64_t pem1:1;
7332 		uint64_t srio0:1;
7333 		uint64_t srio1:1;
7334 		uint64_t lmc0:1;
7335 		uint64_t reserved_53_55:3;
7336 		uint64_t dfm:1;
7337 		uint64_t reserved_57_62:6;
7338 		uint64_t rst:1;
7339 #endif
7340 	} cn63xx;
7341 	struct cvmx_ciu_int_sum1_cn63xx cn63xxp1;
7342 	struct cvmx_ciu_int_sum1_cn66xx {
7343 #ifdef __BIG_ENDIAN_BITFIELD
7344 		uint64_t rst:1;
7345 		uint64_t reserved_62_62:1;
7346 		uint64_t srio3:1;
7347 		uint64_t srio2:1;
7348 		uint64_t reserved_57_59:3;
7349 		uint64_t dfm:1;
7350 		uint64_t reserved_53_55:3;
7351 		uint64_t lmc0:1;
7352 		uint64_t reserved_51_51:1;
7353 		uint64_t srio0:1;
7354 		uint64_t pem1:1;
7355 		uint64_t pem0:1;
7356 		uint64_t ptp:1;
7357 		uint64_t agl:1;
7358 		uint64_t reserved_38_45:8;
7359 		uint64_t agx1:1;
7360 		uint64_t agx0:1;
7361 		uint64_t dpi:1;
7362 		uint64_t sli:1;
7363 		uint64_t usb:1;
7364 		uint64_t dfa:1;
7365 		uint64_t key:1;
7366 		uint64_t rad:1;
7367 		uint64_t tim:1;
7368 		uint64_t zip:1;
7369 		uint64_t pko:1;
7370 		uint64_t pip:1;
7371 		uint64_t ipd:1;
7372 		uint64_t l2c:1;
7373 		uint64_t pow:1;
7374 		uint64_t fpa:1;
7375 		uint64_t iob:1;
7376 		uint64_t mio:1;
7377 		uint64_t nand:1;
7378 		uint64_t mii1:1;
7379 		uint64_t reserved_10_17:8;
7380 		uint64_t wdog:10;
7381 #else
7382 		uint64_t wdog:10;
7383 		uint64_t reserved_10_17:8;
7384 		uint64_t mii1:1;
7385 		uint64_t nand:1;
7386 		uint64_t mio:1;
7387 		uint64_t iob:1;
7388 		uint64_t fpa:1;
7389 		uint64_t pow:1;
7390 		uint64_t l2c:1;
7391 		uint64_t ipd:1;
7392 		uint64_t pip:1;
7393 		uint64_t pko:1;
7394 		uint64_t zip:1;
7395 		uint64_t tim:1;
7396 		uint64_t rad:1;
7397 		uint64_t key:1;
7398 		uint64_t dfa:1;
7399 		uint64_t usb:1;
7400 		uint64_t sli:1;
7401 		uint64_t dpi:1;
7402 		uint64_t agx0:1;
7403 		uint64_t agx1:1;
7404 		uint64_t reserved_38_45:8;
7405 		uint64_t agl:1;
7406 		uint64_t ptp:1;
7407 		uint64_t pem0:1;
7408 		uint64_t pem1:1;
7409 		uint64_t srio0:1;
7410 		uint64_t reserved_51_51:1;
7411 		uint64_t lmc0:1;
7412 		uint64_t reserved_53_55:3;
7413 		uint64_t dfm:1;
7414 		uint64_t reserved_57_59:3;
7415 		uint64_t srio2:1;
7416 		uint64_t srio3:1;
7417 		uint64_t reserved_62_62:1;
7418 		uint64_t rst:1;
7419 #endif
7420 	} cn66xx;
7421 	struct cvmx_ciu_int_sum1_cnf71xx {
7422 #ifdef __BIG_ENDIAN_BITFIELD
7423 		uint64_t rst:1;
7424 		uint64_t reserved_53_62:10;
7425 		uint64_t lmc0:1;
7426 		uint64_t reserved_50_51:2;
7427 		uint64_t pem1:1;
7428 		uint64_t pem0:1;
7429 		uint64_t ptp:1;
7430 		uint64_t reserved_37_46:10;
7431 		uint64_t agx0:1;
7432 		uint64_t dpi:1;
7433 		uint64_t sli:1;
7434 		uint64_t usb:1;
7435 		uint64_t reserved_32_32:1;
7436 		uint64_t key:1;
7437 		uint64_t rad:1;
7438 		uint64_t tim:1;
7439 		uint64_t reserved_28_28:1;
7440 		uint64_t pko:1;
7441 		uint64_t pip:1;
7442 		uint64_t ipd:1;
7443 		uint64_t l2c:1;
7444 		uint64_t pow:1;
7445 		uint64_t fpa:1;
7446 		uint64_t iob:1;
7447 		uint64_t mio:1;
7448 		uint64_t nand:1;
7449 		uint64_t reserved_4_18:15;
7450 		uint64_t wdog:4;
7451 #else
7452 		uint64_t wdog:4;
7453 		uint64_t reserved_4_18:15;
7454 		uint64_t nand:1;
7455 		uint64_t mio:1;
7456 		uint64_t iob:1;
7457 		uint64_t fpa:1;
7458 		uint64_t pow:1;
7459 		uint64_t l2c:1;
7460 		uint64_t ipd:1;
7461 		uint64_t pip:1;
7462 		uint64_t pko:1;
7463 		uint64_t reserved_28_28:1;
7464 		uint64_t tim:1;
7465 		uint64_t rad:1;
7466 		uint64_t key:1;
7467 		uint64_t reserved_32_32:1;
7468 		uint64_t usb:1;
7469 		uint64_t sli:1;
7470 		uint64_t dpi:1;
7471 		uint64_t agx0:1;
7472 		uint64_t reserved_37_46:10;
7473 		uint64_t ptp:1;
7474 		uint64_t pem0:1;
7475 		uint64_t pem1:1;
7476 		uint64_t reserved_50_51:2;
7477 		uint64_t lmc0:1;
7478 		uint64_t reserved_53_62:10;
7479 		uint64_t rst:1;
7480 #endif
7481 	} cnf71xx;
7482 };
7483 
7484 union cvmx_ciu_mbox_clrx {
7485 	uint64_t u64;
7486 	struct cvmx_ciu_mbox_clrx_s {
7487 #ifdef __BIG_ENDIAN_BITFIELD
7488 		uint64_t reserved_32_63:32;
7489 		uint64_t bits:32;
7490 #else
7491 		uint64_t bits:32;
7492 		uint64_t reserved_32_63:32;
7493 #endif
7494 	} s;
7495 	struct cvmx_ciu_mbox_clrx_s cn30xx;
7496 	struct cvmx_ciu_mbox_clrx_s cn31xx;
7497 	struct cvmx_ciu_mbox_clrx_s cn38xx;
7498 	struct cvmx_ciu_mbox_clrx_s cn38xxp2;
7499 	struct cvmx_ciu_mbox_clrx_s cn50xx;
7500 	struct cvmx_ciu_mbox_clrx_s cn52xx;
7501 	struct cvmx_ciu_mbox_clrx_s cn52xxp1;
7502 	struct cvmx_ciu_mbox_clrx_s cn56xx;
7503 	struct cvmx_ciu_mbox_clrx_s cn56xxp1;
7504 	struct cvmx_ciu_mbox_clrx_s cn58xx;
7505 	struct cvmx_ciu_mbox_clrx_s cn58xxp1;
7506 	struct cvmx_ciu_mbox_clrx_s cn61xx;
7507 	struct cvmx_ciu_mbox_clrx_s cn63xx;
7508 	struct cvmx_ciu_mbox_clrx_s cn63xxp1;
7509 	struct cvmx_ciu_mbox_clrx_s cn66xx;
7510 	struct cvmx_ciu_mbox_clrx_s cn68xx;
7511 	struct cvmx_ciu_mbox_clrx_s cn68xxp1;
7512 	struct cvmx_ciu_mbox_clrx_s cnf71xx;
7513 };
7514 
7515 union cvmx_ciu_mbox_setx {
7516 	uint64_t u64;
7517 	struct cvmx_ciu_mbox_setx_s {
7518 #ifdef __BIG_ENDIAN_BITFIELD
7519 		uint64_t reserved_32_63:32;
7520 		uint64_t bits:32;
7521 #else
7522 		uint64_t bits:32;
7523 		uint64_t reserved_32_63:32;
7524 #endif
7525 	} s;
7526 	struct cvmx_ciu_mbox_setx_s cn30xx;
7527 	struct cvmx_ciu_mbox_setx_s cn31xx;
7528 	struct cvmx_ciu_mbox_setx_s cn38xx;
7529 	struct cvmx_ciu_mbox_setx_s cn38xxp2;
7530 	struct cvmx_ciu_mbox_setx_s cn50xx;
7531 	struct cvmx_ciu_mbox_setx_s cn52xx;
7532 	struct cvmx_ciu_mbox_setx_s cn52xxp1;
7533 	struct cvmx_ciu_mbox_setx_s cn56xx;
7534 	struct cvmx_ciu_mbox_setx_s cn56xxp1;
7535 	struct cvmx_ciu_mbox_setx_s cn58xx;
7536 	struct cvmx_ciu_mbox_setx_s cn58xxp1;
7537 	struct cvmx_ciu_mbox_setx_s cn61xx;
7538 	struct cvmx_ciu_mbox_setx_s cn63xx;
7539 	struct cvmx_ciu_mbox_setx_s cn63xxp1;
7540 	struct cvmx_ciu_mbox_setx_s cn66xx;
7541 	struct cvmx_ciu_mbox_setx_s cn68xx;
7542 	struct cvmx_ciu_mbox_setx_s cn68xxp1;
7543 	struct cvmx_ciu_mbox_setx_s cnf71xx;
7544 };
7545 
7546 union cvmx_ciu_nmi {
7547 	uint64_t u64;
7548 	struct cvmx_ciu_nmi_s {
7549 #ifdef __BIG_ENDIAN_BITFIELD
7550 		uint64_t reserved_32_63:32;
7551 		uint64_t nmi:32;
7552 #else
7553 		uint64_t nmi:32;
7554 		uint64_t reserved_32_63:32;
7555 #endif
7556 	} s;
7557 	struct cvmx_ciu_nmi_cn30xx {
7558 #ifdef __BIG_ENDIAN_BITFIELD
7559 		uint64_t reserved_1_63:63;
7560 		uint64_t nmi:1;
7561 #else
7562 		uint64_t nmi:1;
7563 		uint64_t reserved_1_63:63;
7564 #endif
7565 	} cn30xx;
7566 	struct cvmx_ciu_nmi_cn31xx {
7567 #ifdef __BIG_ENDIAN_BITFIELD
7568 		uint64_t reserved_2_63:62;
7569 		uint64_t nmi:2;
7570 #else
7571 		uint64_t nmi:2;
7572 		uint64_t reserved_2_63:62;
7573 #endif
7574 	} cn31xx;
7575 	struct cvmx_ciu_nmi_cn38xx {
7576 #ifdef __BIG_ENDIAN_BITFIELD
7577 		uint64_t reserved_16_63:48;
7578 		uint64_t nmi:16;
7579 #else
7580 		uint64_t nmi:16;
7581 		uint64_t reserved_16_63:48;
7582 #endif
7583 	} cn38xx;
7584 	struct cvmx_ciu_nmi_cn38xx cn38xxp2;
7585 	struct cvmx_ciu_nmi_cn31xx cn50xx;
7586 	struct cvmx_ciu_nmi_cn52xx {
7587 #ifdef __BIG_ENDIAN_BITFIELD
7588 		uint64_t reserved_4_63:60;
7589 		uint64_t nmi:4;
7590 #else
7591 		uint64_t nmi:4;
7592 		uint64_t reserved_4_63:60;
7593 #endif
7594 	} cn52xx;
7595 	struct cvmx_ciu_nmi_cn52xx cn52xxp1;
7596 	struct cvmx_ciu_nmi_cn56xx {
7597 #ifdef __BIG_ENDIAN_BITFIELD
7598 		uint64_t reserved_12_63:52;
7599 		uint64_t nmi:12;
7600 #else
7601 		uint64_t nmi:12;
7602 		uint64_t reserved_12_63:52;
7603 #endif
7604 	} cn56xx;
7605 	struct cvmx_ciu_nmi_cn56xx cn56xxp1;
7606 	struct cvmx_ciu_nmi_cn38xx cn58xx;
7607 	struct cvmx_ciu_nmi_cn38xx cn58xxp1;
7608 	struct cvmx_ciu_nmi_cn52xx cn61xx;
7609 	struct cvmx_ciu_nmi_cn63xx {
7610 #ifdef __BIG_ENDIAN_BITFIELD
7611 		uint64_t reserved_6_63:58;
7612 		uint64_t nmi:6;
7613 #else
7614 		uint64_t nmi:6;
7615 		uint64_t reserved_6_63:58;
7616 #endif
7617 	} cn63xx;
7618 	struct cvmx_ciu_nmi_cn63xx cn63xxp1;
7619 	struct cvmx_ciu_nmi_cn66xx {
7620 #ifdef __BIG_ENDIAN_BITFIELD
7621 		uint64_t reserved_10_63:54;
7622 		uint64_t nmi:10;
7623 #else
7624 		uint64_t nmi:10;
7625 		uint64_t reserved_10_63:54;
7626 #endif
7627 	} cn66xx;
7628 	struct cvmx_ciu_nmi_s cn68xx;
7629 	struct cvmx_ciu_nmi_s cn68xxp1;
7630 	struct cvmx_ciu_nmi_cn52xx cnf71xx;
7631 };
7632 
7633 union cvmx_ciu_pci_inta {
7634 	uint64_t u64;
7635 	struct cvmx_ciu_pci_inta_s {
7636 #ifdef __BIG_ENDIAN_BITFIELD
7637 		uint64_t reserved_2_63:62;
7638 		uint64_t intr:2;
7639 #else
7640 		uint64_t intr:2;
7641 		uint64_t reserved_2_63:62;
7642 #endif
7643 	} s;
7644 	struct cvmx_ciu_pci_inta_s cn30xx;
7645 	struct cvmx_ciu_pci_inta_s cn31xx;
7646 	struct cvmx_ciu_pci_inta_s cn38xx;
7647 	struct cvmx_ciu_pci_inta_s cn38xxp2;
7648 	struct cvmx_ciu_pci_inta_s cn50xx;
7649 	struct cvmx_ciu_pci_inta_s cn52xx;
7650 	struct cvmx_ciu_pci_inta_s cn52xxp1;
7651 	struct cvmx_ciu_pci_inta_s cn56xx;
7652 	struct cvmx_ciu_pci_inta_s cn56xxp1;
7653 	struct cvmx_ciu_pci_inta_s cn58xx;
7654 	struct cvmx_ciu_pci_inta_s cn58xxp1;
7655 	struct cvmx_ciu_pci_inta_s cn61xx;
7656 	struct cvmx_ciu_pci_inta_s cn63xx;
7657 	struct cvmx_ciu_pci_inta_s cn63xxp1;
7658 	struct cvmx_ciu_pci_inta_s cn66xx;
7659 	struct cvmx_ciu_pci_inta_s cn68xx;
7660 	struct cvmx_ciu_pci_inta_s cn68xxp1;
7661 	struct cvmx_ciu_pci_inta_s cnf71xx;
7662 };
7663 
7664 union cvmx_ciu_pp_bist_stat {
7665 	uint64_t u64;
7666 	struct cvmx_ciu_pp_bist_stat_s {
7667 #ifdef __BIG_ENDIAN_BITFIELD
7668 		uint64_t reserved_32_63:32;
7669 		uint64_t pp_bist:32;
7670 #else
7671 		uint64_t pp_bist:32;
7672 		uint64_t reserved_32_63:32;
7673 #endif
7674 	} s;
7675 	struct cvmx_ciu_pp_bist_stat_s cn68xx;
7676 	struct cvmx_ciu_pp_bist_stat_s cn68xxp1;
7677 };
7678 
7679 union cvmx_ciu_pp_dbg {
7680 	uint64_t u64;
7681 	struct cvmx_ciu_pp_dbg_s {
7682 #ifdef __BIG_ENDIAN_BITFIELD
7683 		uint64_t reserved_32_63:32;
7684 		uint64_t ppdbg:32;
7685 #else
7686 		uint64_t ppdbg:32;
7687 		uint64_t reserved_32_63:32;
7688 #endif
7689 	} s;
7690 	struct cvmx_ciu_pp_dbg_cn30xx {
7691 #ifdef __BIG_ENDIAN_BITFIELD
7692 		uint64_t reserved_1_63:63;
7693 		uint64_t ppdbg:1;
7694 #else
7695 		uint64_t ppdbg:1;
7696 		uint64_t reserved_1_63:63;
7697 #endif
7698 	} cn30xx;
7699 	struct cvmx_ciu_pp_dbg_cn31xx {
7700 #ifdef __BIG_ENDIAN_BITFIELD
7701 		uint64_t reserved_2_63:62;
7702 		uint64_t ppdbg:2;
7703 #else
7704 		uint64_t ppdbg:2;
7705 		uint64_t reserved_2_63:62;
7706 #endif
7707 	} cn31xx;
7708 	struct cvmx_ciu_pp_dbg_cn38xx {
7709 #ifdef __BIG_ENDIAN_BITFIELD
7710 		uint64_t reserved_16_63:48;
7711 		uint64_t ppdbg:16;
7712 #else
7713 		uint64_t ppdbg:16;
7714 		uint64_t reserved_16_63:48;
7715 #endif
7716 	} cn38xx;
7717 	struct cvmx_ciu_pp_dbg_cn38xx cn38xxp2;
7718 	struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
7719 	struct cvmx_ciu_pp_dbg_cn52xx {
7720 #ifdef __BIG_ENDIAN_BITFIELD
7721 		uint64_t reserved_4_63:60;
7722 		uint64_t ppdbg:4;
7723 #else
7724 		uint64_t ppdbg:4;
7725 		uint64_t reserved_4_63:60;
7726 #endif
7727 	} cn52xx;
7728 	struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
7729 	struct cvmx_ciu_pp_dbg_cn56xx {
7730 #ifdef __BIG_ENDIAN_BITFIELD
7731 		uint64_t reserved_12_63:52;
7732 		uint64_t ppdbg:12;
7733 #else
7734 		uint64_t ppdbg:12;
7735 		uint64_t reserved_12_63:52;
7736 #endif
7737 	} cn56xx;
7738 	struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
7739 	struct cvmx_ciu_pp_dbg_cn38xx cn58xx;
7740 	struct cvmx_ciu_pp_dbg_cn38xx cn58xxp1;
7741 	struct cvmx_ciu_pp_dbg_cn52xx cn61xx;
7742 	struct cvmx_ciu_pp_dbg_cn63xx {
7743 #ifdef __BIG_ENDIAN_BITFIELD
7744 		uint64_t reserved_6_63:58;
7745 		uint64_t ppdbg:6;
7746 #else
7747 		uint64_t ppdbg:6;
7748 		uint64_t reserved_6_63:58;
7749 #endif
7750 	} cn63xx;
7751 	struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1;
7752 	struct cvmx_ciu_pp_dbg_cn66xx {
7753 #ifdef __BIG_ENDIAN_BITFIELD
7754 		uint64_t reserved_10_63:54;
7755 		uint64_t ppdbg:10;
7756 #else
7757 		uint64_t ppdbg:10;
7758 		uint64_t reserved_10_63:54;
7759 #endif
7760 	} cn66xx;
7761 	struct cvmx_ciu_pp_dbg_s cn68xx;
7762 	struct cvmx_ciu_pp_dbg_s cn68xxp1;
7763 	struct cvmx_ciu_pp_dbg_cn52xx cnf71xx;
7764 };
7765 
7766 union cvmx_ciu_pp_pokex {
7767 	uint64_t u64;
7768 	struct cvmx_ciu_pp_pokex_s {
7769 #ifdef __BIG_ENDIAN_BITFIELD
7770 		uint64_t poke:64;
7771 #else
7772 		uint64_t poke:64;
7773 #endif
7774 	} s;
7775 	struct cvmx_ciu_pp_pokex_s cn30xx;
7776 	struct cvmx_ciu_pp_pokex_s cn31xx;
7777 	struct cvmx_ciu_pp_pokex_s cn38xx;
7778 	struct cvmx_ciu_pp_pokex_s cn38xxp2;
7779 	struct cvmx_ciu_pp_pokex_s cn50xx;
7780 	struct cvmx_ciu_pp_pokex_s cn52xx;
7781 	struct cvmx_ciu_pp_pokex_s cn52xxp1;
7782 	struct cvmx_ciu_pp_pokex_s cn56xx;
7783 	struct cvmx_ciu_pp_pokex_s cn56xxp1;
7784 	struct cvmx_ciu_pp_pokex_s cn58xx;
7785 	struct cvmx_ciu_pp_pokex_s cn58xxp1;
7786 	struct cvmx_ciu_pp_pokex_s cn61xx;
7787 	struct cvmx_ciu_pp_pokex_s cn63xx;
7788 	struct cvmx_ciu_pp_pokex_s cn63xxp1;
7789 	struct cvmx_ciu_pp_pokex_s cn66xx;
7790 	struct cvmx_ciu_pp_pokex_s cn68xx;
7791 	struct cvmx_ciu_pp_pokex_s cn68xxp1;
7792 	struct cvmx_ciu_pp_pokex_s cnf71xx;
7793 };
7794 
7795 union cvmx_ciu_pp_rst {
7796 	uint64_t u64;
7797 	struct cvmx_ciu_pp_rst_s {
7798 #ifdef __BIG_ENDIAN_BITFIELD
7799 		uint64_t reserved_32_63:32;
7800 		uint64_t rst:31;
7801 		uint64_t rst0:1;
7802 #else
7803 		uint64_t rst0:1;
7804 		uint64_t rst:31;
7805 		uint64_t reserved_32_63:32;
7806 #endif
7807 	} s;
7808 	struct cvmx_ciu_pp_rst_cn30xx {
7809 #ifdef __BIG_ENDIAN_BITFIELD
7810 		uint64_t reserved_1_63:63;
7811 		uint64_t rst0:1;
7812 #else
7813 		uint64_t rst0:1;
7814 		uint64_t reserved_1_63:63;
7815 #endif
7816 	} cn30xx;
7817 	struct cvmx_ciu_pp_rst_cn31xx {
7818 #ifdef __BIG_ENDIAN_BITFIELD
7819 		uint64_t reserved_2_63:62;
7820 		uint64_t rst:1;
7821 		uint64_t rst0:1;
7822 #else
7823 		uint64_t rst0:1;
7824 		uint64_t rst:1;
7825 		uint64_t reserved_2_63:62;
7826 #endif
7827 	} cn31xx;
7828 	struct cvmx_ciu_pp_rst_cn38xx {
7829 #ifdef __BIG_ENDIAN_BITFIELD
7830 		uint64_t reserved_16_63:48;
7831 		uint64_t rst:15;
7832 		uint64_t rst0:1;
7833 #else
7834 		uint64_t rst0:1;
7835 		uint64_t rst:15;
7836 		uint64_t reserved_16_63:48;
7837 #endif
7838 	} cn38xx;
7839 	struct cvmx_ciu_pp_rst_cn38xx cn38xxp2;
7840 	struct cvmx_ciu_pp_rst_cn31xx cn50xx;
7841 	struct cvmx_ciu_pp_rst_cn52xx {
7842 #ifdef __BIG_ENDIAN_BITFIELD
7843 		uint64_t reserved_4_63:60;
7844 		uint64_t rst:3;
7845 		uint64_t rst0:1;
7846 #else
7847 		uint64_t rst0:1;
7848 		uint64_t rst:3;
7849 		uint64_t reserved_4_63:60;
7850 #endif
7851 	} cn52xx;
7852 	struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
7853 	struct cvmx_ciu_pp_rst_cn56xx {
7854 #ifdef __BIG_ENDIAN_BITFIELD
7855 		uint64_t reserved_12_63:52;
7856 		uint64_t rst:11;
7857 		uint64_t rst0:1;
7858 #else
7859 		uint64_t rst0:1;
7860 		uint64_t rst:11;
7861 		uint64_t reserved_12_63:52;
7862 #endif
7863 	} cn56xx;
7864 	struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
7865 	struct cvmx_ciu_pp_rst_cn38xx cn58xx;
7866 	struct cvmx_ciu_pp_rst_cn38xx cn58xxp1;
7867 	struct cvmx_ciu_pp_rst_cn52xx cn61xx;
7868 	struct cvmx_ciu_pp_rst_cn63xx {
7869 #ifdef __BIG_ENDIAN_BITFIELD
7870 		uint64_t reserved_6_63:58;
7871 		uint64_t rst:5;
7872 		uint64_t rst0:1;
7873 #else
7874 		uint64_t rst0:1;
7875 		uint64_t rst:5;
7876 		uint64_t reserved_6_63:58;
7877 #endif
7878 	} cn63xx;
7879 	struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
7880 	struct cvmx_ciu_pp_rst_cn66xx {
7881 #ifdef __BIG_ENDIAN_BITFIELD
7882 		uint64_t reserved_10_63:54;
7883 		uint64_t rst:9;
7884 		uint64_t rst0:1;
7885 #else
7886 		uint64_t rst0:1;
7887 		uint64_t rst:9;
7888 		uint64_t reserved_10_63:54;
7889 #endif
7890 	} cn66xx;
7891 	struct cvmx_ciu_pp_rst_s cn68xx;
7892 	struct cvmx_ciu_pp_rst_s cn68xxp1;
7893 	struct cvmx_ciu_pp_rst_cn52xx cnf71xx;
7894 };
7895 
7896 union cvmx_ciu_qlm0 {
7897 	uint64_t u64;
7898 	struct cvmx_ciu_qlm0_s {
7899 #ifdef __BIG_ENDIAN_BITFIELD
7900 		uint64_t g2bypass:1;
7901 		uint64_t reserved_53_62:10;
7902 		uint64_t g2deemph:5;
7903 		uint64_t reserved_45_47:3;
7904 		uint64_t g2margin:5;
7905 		uint64_t reserved_32_39:8;
7906 		uint64_t txbypass:1;
7907 		uint64_t reserved_21_30:10;
7908 		uint64_t txdeemph:5;
7909 		uint64_t reserved_13_15:3;
7910 		uint64_t txmargin:5;
7911 		uint64_t reserved_4_7:4;
7912 		uint64_t lane_en:4;
7913 #else
7914 		uint64_t lane_en:4;
7915 		uint64_t reserved_4_7:4;
7916 		uint64_t txmargin:5;
7917 		uint64_t reserved_13_15:3;
7918 		uint64_t txdeemph:5;
7919 		uint64_t reserved_21_30:10;
7920 		uint64_t txbypass:1;
7921 		uint64_t reserved_32_39:8;
7922 		uint64_t g2margin:5;
7923 		uint64_t reserved_45_47:3;
7924 		uint64_t g2deemph:5;
7925 		uint64_t reserved_53_62:10;
7926 		uint64_t g2bypass:1;
7927 #endif
7928 	} s;
7929 	struct cvmx_ciu_qlm0_s cn61xx;
7930 	struct cvmx_ciu_qlm0_s cn63xx;
7931 	struct cvmx_ciu_qlm0_cn63xxp1 {
7932 #ifdef __BIG_ENDIAN_BITFIELD
7933 		uint64_t reserved_32_63:32;
7934 		uint64_t txbypass:1;
7935 		uint64_t reserved_20_30:11;
7936 		uint64_t txdeemph:4;
7937 		uint64_t reserved_13_15:3;
7938 		uint64_t txmargin:5;
7939 		uint64_t reserved_4_7:4;
7940 		uint64_t lane_en:4;
7941 #else
7942 		uint64_t lane_en:4;
7943 		uint64_t reserved_4_7:4;
7944 		uint64_t txmargin:5;
7945 		uint64_t reserved_13_15:3;
7946 		uint64_t txdeemph:4;
7947 		uint64_t reserved_20_30:11;
7948 		uint64_t txbypass:1;
7949 		uint64_t reserved_32_63:32;
7950 #endif
7951 	} cn63xxp1;
7952 	struct cvmx_ciu_qlm0_s cn66xx;
7953 	struct cvmx_ciu_qlm0_cn68xx {
7954 #ifdef __BIG_ENDIAN_BITFIELD
7955 		uint64_t reserved_32_63:32;
7956 		uint64_t txbypass:1;
7957 		uint64_t reserved_21_30:10;
7958 		uint64_t txdeemph:5;
7959 		uint64_t reserved_13_15:3;
7960 		uint64_t txmargin:5;
7961 		uint64_t reserved_4_7:4;
7962 		uint64_t lane_en:4;
7963 #else
7964 		uint64_t lane_en:4;
7965 		uint64_t reserved_4_7:4;
7966 		uint64_t txmargin:5;
7967 		uint64_t reserved_13_15:3;
7968 		uint64_t txdeemph:5;
7969 		uint64_t reserved_21_30:10;
7970 		uint64_t txbypass:1;
7971 		uint64_t reserved_32_63:32;
7972 #endif
7973 	} cn68xx;
7974 	struct cvmx_ciu_qlm0_cn68xx cn68xxp1;
7975 	struct cvmx_ciu_qlm0_s cnf71xx;
7976 };
7977 
7978 union cvmx_ciu_qlm1 {
7979 	uint64_t u64;
7980 	struct cvmx_ciu_qlm1_s {
7981 #ifdef __BIG_ENDIAN_BITFIELD
7982 		uint64_t g2bypass:1;
7983 		uint64_t reserved_53_62:10;
7984 		uint64_t g2deemph:5;
7985 		uint64_t reserved_45_47:3;
7986 		uint64_t g2margin:5;
7987 		uint64_t reserved_32_39:8;
7988 		uint64_t txbypass:1;
7989 		uint64_t reserved_21_30:10;
7990 		uint64_t txdeemph:5;
7991 		uint64_t reserved_13_15:3;
7992 		uint64_t txmargin:5;
7993 		uint64_t reserved_4_7:4;
7994 		uint64_t lane_en:4;
7995 #else
7996 		uint64_t lane_en:4;
7997 		uint64_t reserved_4_7:4;
7998 		uint64_t txmargin:5;
7999 		uint64_t reserved_13_15:3;
8000 		uint64_t txdeemph:5;
8001 		uint64_t reserved_21_30:10;
8002 		uint64_t txbypass:1;
8003 		uint64_t reserved_32_39:8;
8004 		uint64_t g2margin:5;
8005 		uint64_t reserved_45_47:3;
8006 		uint64_t g2deemph:5;
8007 		uint64_t reserved_53_62:10;
8008 		uint64_t g2bypass:1;
8009 #endif
8010 	} s;
8011 	struct cvmx_ciu_qlm1_s cn61xx;
8012 	struct cvmx_ciu_qlm1_s cn63xx;
8013 	struct cvmx_ciu_qlm1_cn63xxp1 {
8014 #ifdef __BIG_ENDIAN_BITFIELD
8015 		uint64_t reserved_32_63:32;
8016 		uint64_t txbypass:1;
8017 		uint64_t reserved_20_30:11;
8018 		uint64_t txdeemph:4;
8019 		uint64_t reserved_13_15:3;
8020 		uint64_t txmargin:5;
8021 		uint64_t reserved_4_7:4;
8022 		uint64_t lane_en:4;
8023 #else
8024 		uint64_t lane_en:4;
8025 		uint64_t reserved_4_7:4;
8026 		uint64_t txmargin:5;
8027 		uint64_t reserved_13_15:3;
8028 		uint64_t txdeemph:4;
8029 		uint64_t reserved_20_30:11;
8030 		uint64_t txbypass:1;
8031 		uint64_t reserved_32_63:32;
8032 #endif
8033 	} cn63xxp1;
8034 	struct cvmx_ciu_qlm1_s cn66xx;
8035 	struct cvmx_ciu_qlm1_s cn68xx;
8036 	struct cvmx_ciu_qlm1_s cn68xxp1;
8037 	struct cvmx_ciu_qlm1_s cnf71xx;
8038 };
8039 
8040 union cvmx_ciu_qlm2 {
8041 	uint64_t u64;
8042 	struct cvmx_ciu_qlm2_s {
8043 #ifdef __BIG_ENDIAN_BITFIELD
8044 		uint64_t g2bypass:1;
8045 		uint64_t reserved_53_62:10;
8046 		uint64_t g2deemph:5;
8047 		uint64_t reserved_45_47:3;
8048 		uint64_t g2margin:5;
8049 		uint64_t reserved_32_39:8;
8050 		uint64_t txbypass:1;
8051 		uint64_t reserved_21_30:10;
8052 		uint64_t txdeemph:5;
8053 		uint64_t reserved_13_15:3;
8054 		uint64_t txmargin:5;
8055 		uint64_t reserved_4_7:4;
8056 		uint64_t lane_en:4;
8057 #else
8058 		uint64_t lane_en:4;
8059 		uint64_t reserved_4_7:4;
8060 		uint64_t txmargin:5;
8061 		uint64_t reserved_13_15:3;
8062 		uint64_t txdeemph:5;
8063 		uint64_t reserved_21_30:10;
8064 		uint64_t txbypass:1;
8065 		uint64_t reserved_32_39:8;
8066 		uint64_t g2margin:5;
8067 		uint64_t reserved_45_47:3;
8068 		uint64_t g2deemph:5;
8069 		uint64_t reserved_53_62:10;
8070 		uint64_t g2bypass:1;
8071 #endif
8072 	} s;
8073 	struct cvmx_ciu_qlm2_cn61xx {
8074 #ifdef __BIG_ENDIAN_BITFIELD
8075 		uint64_t reserved_32_63:32;
8076 		uint64_t txbypass:1;
8077 		uint64_t reserved_21_30:10;
8078 		uint64_t txdeemph:5;
8079 		uint64_t reserved_13_15:3;
8080 		uint64_t txmargin:5;
8081 		uint64_t reserved_4_7:4;
8082 		uint64_t lane_en:4;
8083 #else
8084 		uint64_t lane_en:4;
8085 		uint64_t reserved_4_7:4;
8086 		uint64_t txmargin:5;
8087 		uint64_t reserved_13_15:3;
8088 		uint64_t txdeemph:5;
8089 		uint64_t reserved_21_30:10;
8090 		uint64_t txbypass:1;
8091 		uint64_t reserved_32_63:32;
8092 #endif
8093 	} cn61xx;
8094 	struct cvmx_ciu_qlm2_cn61xx cn63xx;
8095 	struct cvmx_ciu_qlm2_cn63xxp1 {
8096 #ifdef __BIG_ENDIAN_BITFIELD
8097 		uint64_t reserved_32_63:32;
8098 		uint64_t txbypass:1;
8099 		uint64_t reserved_20_30:11;
8100 		uint64_t txdeemph:4;
8101 		uint64_t reserved_13_15:3;
8102 		uint64_t txmargin:5;
8103 		uint64_t reserved_4_7:4;
8104 		uint64_t lane_en:4;
8105 #else
8106 		uint64_t lane_en:4;
8107 		uint64_t reserved_4_7:4;
8108 		uint64_t txmargin:5;
8109 		uint64_t reserved_13_15:3;
8110 		uint64_t txdeemph:4;
8111 		uint64_t reserved_20_30:11;
8112 		uint64_t txbypass:1;
8113 		uint64_t reserved_32_63:32;
8114 #endif
8115 	} cn63xxp1;
8116 	struct cvmx_ciu_qlm2_cn61xx cn66xx;
8117 	struct cvmx_ciu_qlm2_s cn68xx;
8118 	struct cvmx_ciu_qlm2_s cn68xxp1;
8119 	struct cvmx_ciu_qlm2_cn61xx cnf71xx;
8120 };
8121 
8122 union cvmx_ciu_qlm3 {
8123 	uint64_t u64;
8124 	struct cvmx_ciu_qlm3_s {
8125 #ifdef __BIG_ENDIAN_BITFIELD
8126 		uint64_t g2bypass:1;
8127 		uint64_t reserved_53_62:10;
8128 		uint64_t g2deemph:5;
8129 		uint64_t reserved_45_47:3;
8130 		uint64_t g2margin:5;
8131 		uint64_t reserved_32_39:8;
8132 		uint64_t txbypass:1;
8133 		uint64_t reserved_21_30:10;
8134 		uint64_t txdeemph:5;
8135 		uint64_t reserved_13_15:3;
8136 		uint64_t txmargin:5;
8137 		uint64_t reserved_4_7:4;
8138 		uint64_t lane_en:4;
8139 #else
8140 		uint64_t lane_en:4;
8141 		uint64_t reserved_4_7:4;
8142 		uint64_t txmargin:5;
8143 		uint64_t reserved_13_15:3;
8144 		uint64_t txdeemph:5;
8145 		uint64_t reserved_21_30:10;
8146 		uint64_t txbypass:1;
8147 		uint64_t reserved_32_39:8;
8148 		uint64_t g2margin:5;
8149 		uint64_t reserved_45_47:3;
8150 		uint64_t g2deemph:5;
8151 		uint64_t reserved_53_62:10;
8152 		uint64_t g2bypass:1;
8153 #endif
8154 	} s;
8155 	struct cvmx_ciu_qlm3_s cn68xx;
8156 	struct cvmx_ciu_qlm3_s cn68xxp1;
8157 };
8158 
8159 union cvmx_ciu_qlm4 {
8160 	uint64_t u64;
8161 	struct cvmx_ciu_qlm4_s {
8162 #ifdef __BIG_ENDIAN_BITFIELD
8163 		uint64_t g2bypass:1;
8164 		uint64_t reserved_53_62:10;
8165 		uint64_t g2deemph:5;
8166 		uint64_t reserved_45_47:3;
8167 		uint64_t g2margin:5;
8168 		uint64_t reserved_32_39:8;
8169 		uint64_t txbypass:1;
8170 		uint64_t reserved_21_30:10;
8171 		uint64_t txdeemph:5;
8172 		uint64_t reserved_13_15:3;
8173 		uint64_t txmargin:5;
8174 		uint64_t reserved_4_7:4;
8175 		uint64_t lane_en:4;
8176 #else
8177 		uint64_t lane_en:4;
8178 		uint64_t reserved_4_7:4;
8179 		uint64_t txmargin:5;
8180 		uint64_t reserved_13_15:3;
8181 		uint64_t txdeemph:5;
8182 		uint64_t reserved_21_30:10;
8183 		uint64_t txbypass:1;
8184 		uint64_t reserved_32_39:8;
8185 		uint64_t g2margin:5;
8186 		uint64_t reserved_45_47:3;
8187 		uint64_t g2deemph:5;
8188 		uint64_t reserved_53_62:10;
8189 		uint64_t g2bypass:1;
8190 #endif
8191 	} s;
8192 	struct cvmx_ciu_qlm4_s cn68xx;
8193 	struct cvmx_ciu_qlm4_s cn68xxp1;
8194 };
8195 
8196 union cvmx_ciu_qlm_dcok {
8197 	uint64_t u64;
8198 	struct cvmx_ciu_qlm_dcok_s {
8199 #ifdef __BIG_ENDIAN_BITFIELD
8200 		uint64_t reserved_4_63:60;
8201 		uint64_t qlm_dcok:4;
8202 #else
8203 		uint64_t qlm_dcok:4;
8204 		uint64_t reserved_4_63:60;
8205 #endif
8206 	} s;
8207 	struct cvmx_ciu_qlm_dcok_cn52xx {
8208 #ifdef __BIG_ENDIAN_BITFIELD
8209 		uint64_t reserved_2_63:62;
8210 		uint64_t qlm_dcok:2;
8211 #else
8212 		uint64_t qlm_dcok:2;
8213 		uint64_t reserved_2_63:62;
8214 #endif
8215 	} cn52xx;
8216 	struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
8217 	struct cvmx_ciu_qlm_dcok_s cn56xx;
8218 	struct cvmx_ciu_qlm_dcok_s cn56xxp1;
8219 };
8220 
8221 union cvmx_ciu_qlm_jtgc {
8222 	uint64_t u64;
8223 	struct cvmx_ciu_qlm_jtgc_s {
8224 #ifdef __BIG_ENDIAN_BITFIELD
8225 		uint64_t reserved_17_63:47;
8226 		uint64_t bypass_ext:1;
8227 		uint64_t reserved_11_15:5;
8228 		uint64_t clk_div:3;
8229 		uint64_t reserved_7_7:1;
8230 		uint64_t mux_sel:3;
8231 		uint64_t bypass:4;
8232 #else
8233 		uint64_t bypass:4;
8234 		uint64_t mux_sel:3;
8235 		uint64_t reserved_7_7:1;
8236 		uint64_t clk_div:3;
8237 		uint64_t reserved_11_15:5;
8238 		uint64_t bypass_ext:1;
8239 		uint64_t reserved_17_63:47;
8240 #endif
8241 	} s;
8242 	struct cvmx_ciu_qlm_jtgc_cn52xx {
8243 #ifdef __BIG_ENDIAN_BITFIELD
8244 		uint64_t reserved_11_63:53;
8245 		uint64_t clk_div:3;
8246 		uint64_t reserved_5_7:3;
8247 		uint64_t mux_sel:1;
8248 		uint64_t reserved_2_3:2;
8249 		uint64_t bypass:2;
8250 #else
8251 		uint64_t bypass:2;
8252 		uint64_t reserved_2_3:2;
8253 		uint64_t mux_sel:1;
8254 		uint64_t reserved_5_7:3;
8255 		uint64_t clk_div:3;
8256 		uint64_t reserved_11_63:53;
8257 #endif
8258 	} cn52xx;
8259 	struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
8260 	struct cvmx_ciu_qlm_jtgc_cn56xx {
8261 #ifdef __BIG_ENDIAN_BITFIELD
8262 		uint64_t reserved_11_63:53;
8263 		uint64_t clk_div:3;
8264 		uint64_t reserved_6_7:2;
8265 		uint64_t mux_sel:2;
8266 		uint64_t bypass:4;
8267 #else
8268 		uint64_t bypass:4;
8269 		uint64_t mux_sel:2;
8270 		uint64_t reserved_6_7:2;
8271 		uint64_t clk_div:3;
8272 		uint64_t reserved_11_63:53;
8273 #endif
8274 	} cn56xx;
8275 	struct cvmx_ciu_qlm_jtgc_cn56xx cn56xxp1;
8276 	struct cvmx_ciu_qlm_jtgc_cn61xx {
8277 #ifdef __BIG_ENDIAN_BITFIELD
8278 		uint64_t reserved_11_63:53;
8279 		uint64_t clk_div:3;
8280 		uint64_t reserved_6_7:2;
8281 		uint64_t mux_sel:2;
8282 		uint64_t reserved_3_3:1;
8283 		uint64_t bypass:3;
8284 #else
8285 		uint64_t bypass:3;
8286 		uint64_t reserved_3_3:1;
8287 		uint64_t mux_sel:2;
8288 		uint64_t reserved_6_7:2;
8289 		uint64_t clk_div:3;
8290 		uint64_t reserved_11_63:53;
8291 #endif
8292 	} cn61xx;
8293 	struct cvmx_ciu_qlm_jtgc_cn61xx cn63xx;
8294 	struct cvmx_ciu_qlm_jtgc_cn61xx cn63xxp1;
8295 	struct cvmx_ciu_qlm_jtgc_cn61xx cn66xx;
8296 	struct cvmx_ciu_qlm_jtgc_s cn68xx;
8297 	struct cvmx_ciu_qlm_jtgc_s cn68xxp1;
8298 	struct cvmx_ciu_qlm_jtgc_cn61xx cnf71xx;
8299 };
8300 
8301 union cvmx_ciu_qlm_jtgd {
8302 	uint64_t u64;
8303 	struct cvmx_ciu_qlm_jtgd_s {
8304 #ifdef __BIG_ENDIAN_BITFIELD
8305 		uint64_t capture:1;
8306 		uint64_t shift:1;
8307 		uint64_t update:1;
8308 		uint64_t reserved_45_60:16;
8309 		uint64_t select:5;
8310 		uint64_t reserved_37_39:3;
8311 		uint64_t shft_cnt:5;
8312 		uint64_t shft_reg:32;
8313 #else
8314 		uint64_t shft_reg:32;
8315 		uint64_t shft_cnt:5;
8316 		uint64_t reserved_37_39:3;
8317 		uint64_t select:5;
8318 		uint64_t reserved_45_60:16;
8319 		uint64_t update:1;
8320 		uint64_t shift:1;
8321 		uint64_t capture:1;
8322 #endif
8323 	} s;
8324 	struct cvmx_ciu_qlm_jtgd_cn52xx {
8325 #ifdef __BIG_ENDIAN_BITFIELD
8326 		uint64_t capture:1;
8327 		uint64_t shift:1;
8328 		uint64_t update:1;
8329 		uint64_t reserved_42_60:19;
8330 		uint64_t select:2;
8331 		uint64_t reserved_37_39:3;
8332 		uint64_t shft_cnt:5;
8333 		uint64_t shft_reg:32;
8334 #else
8335 		uint64_t shft_reg:32;
8336 		uint64_t shft_cnt:5;
8337 		uint64_t reserved_37_39:3;
8338 		uint64_t select:2;
8339 		uint64_t reserved_42_60:19;
8340 		uint64_t update:1;
8341 		uint64_t shift:1;
8342 		uint64_t capture:1;
8343 #endif
8344 	} cn52xx;
8345 	struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
8346 	struct cvmx_ciu_qlm_jtgd_cn56xx {
8347 #ifdef __BIG_ENDIAN_BITFIELD
8348 		uint64_t capture:1;
8349 		uint64_t shift:1;
8350 		uint64_t update:1;
8351 		uint64_t reserved_44_60:17;
8352 		uint64_t select:4;
8353 		uint64_t reserved_37_39:3;
8354 		uint64_t shft_cnt:5;
8355 		uint64_t shft_reg:32;
8356 #else
8357 		uint64_t shft_reg:32;
8358 		uint64_t shft_cnt:5;
8359 		uint64_t reserved_37_39:3;
8360 		uint64_t select:4;
8361 		uint64_t reserved_44_60:17;
8362 		uint64_t update:1;
8363 		uint64_t shift:1;
8364 		uint64_t capture:1;
8365 #endif
8366 	} cn56xx;
8367 	struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
8368 #ifdef __BIG_ENDIAN_BITFIELD
8369 		uint64_t capture:1;
8370 		uint64_t shift:1;
8371 		uint64_t update:1;
8372 		uint64_t reserved_37_60:24;
8373 		uint64_t shft_cnt:5;
8374 		uint64_t shft_reg:32;
8375 #else
8376 		uint64_t shft_reg:32;
8377 		uint64_t shft_cnt:5;
8378 		uint64_t reserved_37_60:24;
8379 		uint64_t update:1;
8380 		uint64_t shift:1;
8381 		uint64_t capture:1;
8382 #endif
8383 	} cn56xxp1;
8384 	struct cvmx_ciu_qlm_jtgd_cn61xx {
8385 #ifdef __BIG_ENDIAN_BITFIELD
8386 		uint64_t capture:1;
8387 		uint64_t shift:1;
8388 		uint64_t update:1;
8389 		uint64_t reserved_43_60:18;
8390 		uint64_t select:3;
8391 		uint64_t reserved_37_39:3;
8392 		uint64_t shft_cnt:5;
8393 		uint64_t shft_reg:32;
8394 #else
8395 		uint64_t shft_reg:32;
8396 		uint64_t shft_cnt:5;
8397 		uint64_t reserved_37_39:3;
8398 		uint64_t select:3;
8399 		uint64_t reserved_43_60:18;
8400 		uint64_t update:1;
8401 		uint64_t shift:1;
8402 		uint64_t capture:1;
8403 #endif
8404 	} cn61xx;
8405 	struct cvmx_ciu_qlm_jtgd_cn61xx cn63xx;
8406 	struct cvmx_ciu_qlm_jtgd_cn61xx cn63xxp1;
8407 	struct cvmx_ciu_qlm_jtgd_cn61xx cn66xx;
8408 	struct cvmx_ciu_qlm_jtgd_s cn68xx;
8409 	struct cvmx_ciu_qlm_jtgd_s cn68xxp1;
8410 	struct cvmx_ciu_qlm_jtgd_cn61xx cnf71xx;
8411 };
8412 
8413 union cvmx_ciu_soft_bist {
8414 	uint64_t u64;
8415 	struct cvmx_ciu_soft_bist_s {
8416 #ifdef __BIG_ENDIAN_BITFIELD
8417 		uint64_t reserved_1_63:63;
8418 		uint64_t soft_bist:1;
8419 #else
8420 		uint64_t soft_bist:1;
8421 		uint64_t reserved_1_63:63;
8422 #endif
8423 	} s;
8424 	struct cvmx_ciu_soft_bist_s cn30xx;
8425 	struct cvmx_ciu_soft_bist_s cn31xx;
8426 	struct cvmx_ciu_soft_bist_s cn38xx;
8427 	struct cvmx_ciu_soft_bist_s cn38xxp2;
8428 	struct cvmx_ciu_soft_bist_s cn50xx;
8429 	struct cvmx_ciu_soft_bist_s cn52xx;
8430 	struct cvmx_ciu_soft_bist_s cn52xxp1;
8431 	struct cvmx_ciu_soft_bist_s cn56xx;
8432 	struct cvmx_ciu_soft_bist_s cn56xxp1;
8433 	struct cvmx_ciu_soft_bist_s cn58xx;
8434 	struct cvmx_ciu_soft_bist_s cn58xxp1;
8435 	struct cvmx_ciu_soft_bist_s cn61xx;
8436 	struct cvmx_ciu_soft_bist_s cn63xx;
8437 	struct cvmx_ciu_soft_bist_s cn63xxp1;
8438 	struct cvmx_ciu_soft_bist_s cn66xx;
8439 	struct cvmx_ciu_soft_bist_s cn68xx;
8440 	struct cvmx_ciu_soft_bist_s cn68xxp1;
8441 	struct cvmx_ciu_soft_bist_s cnf71xx;
8442 };
8443 
8444 union cvmx_ciu_soft_prst {
8445 	uint64_t u64;
8446 	struct cvmx_ciu_soft_prst_s {
8447 #ifdef __BIG_ENDIAN_BITFIELD
8448 		uint64_t reserved_3_63:61;
8449 		uint64_t host64:1;
8450 		uint64_t npi:1;
8451 		uint64_t soft_prst:1;
8452 #else
8453 		uint64_t soft_prst:1;
8454 		uint64_t npi:1;
8455 		uint64_t host64:1;
8456 		uint64_t reserved_3_63:61;
8457 #endif
8458 	} s;
8459 	struct cvmx_ciu_soft_prst_s cn30xx;
8460 	struct cvmx_ciu_soft_prst_s cn31xx;
8461 	struct cvmx_ciu_soft_prst_s cn38xx;
8462 	struct cvmx_ciu_soft_prst_s cn38xxp2;
8463 	struct cvmx_ciu_soft_prst_s cn50xx;
8464 	struct cvmx_ciu_soft_prst_cn52xx {
8465 #ifdef __BIG_ENDIAN_BITFIELD
8466 		uint64_t reserved_1_63:63;
8467 		uint64_t soft_prst:1;
8468 #else
8469 		uint64_t soft_prst:1;
8470 		uint64_t reserved_1_63:63;
8471 #endif
8472 	} cn52xx;
8473 	struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
8474 	struct cvmx_ciu_soft_prst_cn52xx cn56xx;
8475 	struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
8476 	struct cvmx_ciu_soft_prst_s cn58xx;
8477 	struct cvmx_ciu_soft_prst_s cn58xxp1;
8478 	struct cvmx_ciu_soft_prst_cn52xx cn61xx;
8479 	struct cvmx_ciu_soft_prst_cn52xx cn63xx;
8480 	struct cvmx_ciu_soft_prst_cn52xx cn63xxp1;
8481 	struct cvmx_ciu_soft_prst_cn52xx cn66xx;
8482 	struct cvmx_ciu_soft_prst_cn52xx cn68xx;
8483 	struct cvmx_ciu_soft_prst_cn52xx cn68xxp1;
8484 	struct cvmx_ciu_soft_prst_cn52xx cnf71xx;
8485 };
8486 
8487 union cvmx_ciu_soft_prst1 {
8488 	uint64_t u64;
8489 	struct cvmx_ciu_soft_prst1_s {
8490 #ifdef __BIG_ENDIAN_BITFIELD
8491 		uint64_t reserved_1_63:63;
8492 		uint64_t soft_prst:1;
8493 #else
8494 		uint64_t soft_prst:1;
8495 		uint64_t reserved_1_63:63;
8496 #endif
8497 	} s;
8498 	struct cvmx_ciu_soft_prst1_s cn52xx;
8499 	struct cvmx_ciu_soft_prst1_s cn52xxp1;
8500 	struct cvmx_ciu_soft_prst1_s cn56xx;
8501 	struct cvmx_ciu_soft_prst1_s cn56xxp1;
8502 	struct cvmx_ciu_soft_prst1_s cn61xx;
8503 	struct cvmx_ciu_soft_prst1_s cn63xx;
8504 	struct cvmx_ciu_soft_prst1_s cn63xxp1;
8505 	struct cvmx_ciu_soft_prst1_s cn66xx;
8506 	struct cvmx_ciu_soft_prst1_s cn68xx;
8507 	struct cvmx_ciu_soft_prst1_s cn68xxp1;
8508 	struct cvmx_ciu_soft_prst1_s cnf71xx;
8509 };
8510 
8511 union cvmx_ciu_soft_prst2 {
8512 	uint64_t u64;
8513 	struct cvmx_ciu_soft_prst2_s {
8514 #ifdef __BIG_ENDIAN_BITFIELD
8515 		uint64_t reserved_1_63:63;
8516 		uint64_t soft_prst:1;
8517 #else
8518 		uint64_t soft_prst:1;
8519 		uint64_t reserved_1_63:63;
8520 #endif
8521 	} s;
8522 	struct cvmx_ciu_soft_prst2_s cn66xx;
8523 };
8524 
8525 union cvmx_ciu_soft_prst3 {
8526 	uint64_t u64;
8527 	struct cvmx_ciu_soft_prst3_s {
8528 #ifdef __BIG_ENDIAN_BITFIELD
8529 		uint64_t reserved_1_63:63;
8530 		uint64_t soft_prst:1;
8531 #else
8532 		uint64_t soft_prst:1;
8533 		uint64_t reserved_1_63:63;
8534 #endif
8535 	} s;
8536 	struct cvmx_ciu_soft_prst3_s cn66xx;
8537 };
8538 
8539 union cvmx_ciu_soft_rst {
8540 	uint64_t u64;
8541 	struct cvmx_ciu_soft_rst_s {
8542 #ifdef __BIG_ENDIAN_BITFIELD
8543 		uint64_t reserved_1_63:63;
8544 		uint64_t soft_rst:1;
8545 #else
8546 		uint64_t soft_rst:1;
8547 		uint64_t reserved_1_63:63;
8548 #endif
8549 	} s;
8550 	struct cvmx_ciu_soft_rst_s cn30xx;
8551 	struct cvmx_ciu_soft_rst_s cn31xx;
8552 	struct cvmx_ciu_soft_rst_s cn38xx;
8553 	struct cvmx_ciu_soft_rst_s cn38xxp2;
8554 	struct cvmx_ciu_soft_rst_s cn50xx;
8555 	struct cvmx_ciu_soft_rst_s cn52xx;
8556 	struct cvmx_ciu_soft_rst_s cn52xxp1;
8557 	struct cvmx_ciu_soft_rst_s cn56xx;
8558 	struct cvmx_ciu_soft_rst_s cn56xxp1;
8559 	struct cvmx_ciu_soft_rst_s cn58xx;
8560 	struct cvmx_ciu_soft_rst_s cn58xxp1;
8561 	struct cvmx_ciu_soft_rst_s cn61xx;
8562 	struct cvmx_ciu_soft_rst_s cn63xx;
8563 	struct cvmx_ciu_soft_rst_s cn63xxp1;
8564 	struct cvmx_ciu_soft_rst_s cn66xx;
8565 	struct cvmx_ciu_soft_rst_s cn68xx;
8566 	struct cvmx_ciu_soft_rst_s cn68xxp1;
8567 	struct cvmx_ciu_soft_rst_s cnf71xx;
8568 };
8569 
8570 union cvmx_ciu_sum1_iox_int {
8571 	uint64_t u64;
8572 	struct cvmx_ciu_sum1_iox_int_s {
8573 #ifdef __BIG_ENDIAN_BITFIELD
8574 		uint64_t rst:1;
8575 		uint64_t reserved_62_62:1;
8576 		uint64_t srio3:1;
8577 		uint64_t srio2:1;
8578 		uint64_t reserved_57_59:3;
8579 		uint64_t dfm:1;
8580 		uint64_t reserved_53_55:3;
8581 		uint64_t lmc0:1;
8582 		uint64_t reserved_51_51:1;
8583 		uint64_t srio0:1;
8584 		uint64_t pem1:1;
8585 		uint64_t pem0:1;
8586 		uint64_t ptp:1;
8587 		uint64_t agl:1;
8588 		uint64_t reserved_41_45:5;
8589 		uint64_t dpi_dma:1;
8590 		uint64_t reserved_38_39:2;
8591 		uint64_t agx1:1;
8592 		uint64_t agx0:1;
8593 		uint64_t dpi:1;
8594 		uint64_t sli:1;
8595 		uint64_t usb:1;
8596 		uint64_t dfa:1;
8597 		uint64_t key:1;
8598 		uint64_t rad:1;
8599 		uint64_t tim:1;
8600 		uint64_t zip:1;
8601 		uint64_t pko:1;
8602 		uint64_t pip:1;
8603 		uint64_t ipd:1;
8604 		uint64_t l2c:1;
8605 		uint64_t pow:1;
8606 		uint64_t fpa:1;
8607 		uint64_t iob:1;
8608 		uint64_t mio:1;
8609 		uint64_t nand:1;
8610 		uint64_t mii1:1;
8611 		uint64_t reserved_10_17:8;
8612 		uint64_t wdog:10;
8613 #else
8614 		uint64_t wdog:10;
8615 		uint64_t reserved_10_17:8;
8616 		uint64_t mii1:1;
8617 		uint64_t nand:1;
8618 		uint64_t mio:1;
8619 		uint64_t iob:1;
8620 		uint64_t fpa:1;
8621 		uint64_t pow:1;
8622 		uint64_t l2c:1;
8623 		uint64_t ipd:1;
8624 		uint64_t pip:1;
8625 		uint64_t pko:1;
8626 		uint64_t zip:1;
8627 		uint64_t tim:1;
8628 		uint64_t rad:1;
8629 		uint64_t key:1;
8630 		uint64_t dfa:1;
8631 		uint64_t usb:1;
8632 		uint64_t sli:1;
8633 		uint64_t dpi:1;
8634 		uint64_t agx0:1;
8635 		uint64_t agx1:1;
8636 		uint64_t reserved_38_39:2;
8637 		uint64_t dpi_dma:1;
8638 		uint64_t reserved_41_45:5;
8639 		uint64_t agl:1;
8640 		uint64_t ptp:1;
8641 		uint64_t pem0:1;
8642 		uint64_t pem1:1;
8643 		uint64_t srio0:1;
8644 		uint64_t reserved_51_51:1;
8645 		uint64_t lmc0:1;
8646 		uint64_t reserved_53_55:3;
8647 		uint64_t dfm:1;
8648 		uint64_t reserved_57_59:3;
8649 		uint64_t srio2:1;
8650 		uint64_t srio3:1;
8651 		uint64_t reserved_62_62:1;
8652 		uint64_t rst:1;
8653 #endif
8654 	} s;
8655 	struct cvmx_ciu_sum1_iox_int_cn61xx {
8656 #ifdef __BIG_ENDIAN_BITFIELD
8657 		uint64_t rst:1;
8658 		uint64_t reserved_53_62:10;
8659 		uint64_t lmc0:1;
8660 		uint64_t reserved_50_51:2;
8661 		uint64_t pem1:1;
8662 		uint64_t pem0:1;
8663 		uint64_t ptp:1;
8664 		uint64_t agl:1;
8665 		uint64_t reserved_41_45:5;
8666 		uint64_t dpi_dma:1;
8667 		uint64_t reserved_38_39:2;
8668 		uint64_t agx1:1;
8669 		uint64_t agx0:1;
8670 		uint64_t dpi:1;
8671 		uint64_t sli:1;
8672 		uint64_t usb:1;
8673 		uint64_t dfa:1;
8674 		uint64_t key:1;
8675 		uint64_t rad:1;
8676 		uint64_t tim:1;
8677 		uint64_t zip:1;
8678 		uint64_t pko:1;
8679 		uint64_t pip:1;
8680 		uint64_t ipd:1;
8681 		uint64_t l2c:1;
8682 		uint64_t pow:1;
8683 		uint64_t fpa:1;
8684 		uint64_t iob:1;
8685 		uint64_t mio:1;
8686 		uint64_t nand:1;
8687 		uint64_t mii1:1;
8688 		uint64_t reserved_4_17:14;
8689 		uint64_t wdog:4;
8690 #else
8691 		uint64_t wdog:4;
8692 		uint64_t reserved_4_17:14;
8693 		uint64_t mii1:1;
8694 		uint64_t nand:1;
8695 		uint64_t mio:1;
8696 		uint64_t iob:1;
8697 		uint64_t fpa:1;
8698 		uint64_t pow:1;
8699 		uint64_t l2c:1;
8700 		uint64_t ipd:1;
8701 		uint64_t pip:1;
8702 		uint64_t pko:1;
8703 		uint64_t zip:1;
8704 		uint64_t tim:1;
8705 		uint64_t rad:1;
8706 		uint64_t key:1;
8707 		uint64_t dfa:1;
8708 		uint64_t usb:1;
8709 		uint64_t sli:1;
8710 		uint64_t dpi:1;
8711 		uint64_t agx0:1;
8712 		uint64_t agx1:1;
8713 		uint64_t reserved_38_39:2;
8714 		uint64_t dpi_dma:1;
8715 		uint64_t reserved_41_45:5;
8716 		uint64_t agl:1;
8717 		uint64_t ptp:1;
8718 		uint64_t pem0:1;
8719 		uint64_t pem1:1;
8720 		uint64_t reserved_50_51:2;
8721 		uint64_t lmc0:1;
8722 		uint64_t reserved_53_62:10;
8723 		uint64_t rst:1;
8724 #endif
8725 	} cn61xx;
8726 	struct cvmx_ciu_sum1_iox_int_cn66xx {
8727 #ifdef __BIG_ENDIAN_BITFIELD
8728 		uint64_t rst:1;
8729 		uint64_t reserved_62_62:1;
8730 		uint64_t srio3:1;
8731 		uint64_t srio2:1;
8732 		uint64_t reserved_57_59:3;
8733 		uint64_t dfm:1;
8734 		uint64_t reserved_53_55:3;
8735 		uint64_t lmc0:1;
8736 		uint64_t reserved_51_51:1;
8737 		uint64_t srio0:1;
8738 		uint64_t pem1:1;
8739 		uint64_t pem0:1;
8740 		uint64_t ptp:1;
8741 		uint64_t agl:1;
8742 		uint64_t reserved_38_45:8;
8743 		uint64_t agx1:1;
8744 		uint64_t agx0:1;
8745 		uint64_t dpi:1;
8746 		uint64_t sli:1;
8747 		uint64_t usb:1;
8748 		uint64_t dfa:1;
8749 		uint64_t key:1;
8750 		uint64_t rad:1;
8751 		uint64_t tim:1;
8752 		uint64_t zip:1;
8753 		uint64_t pko:1;
8754 		uint64_t pip:1;
8755 		uint64_t ipd:1;
8756 		uint64_t l2c:1;
8757 		uint64_t pow:1;
8758 		uint64_t fpa:1;
8759 		uint64_t iob:1;
8760 		uint64_t mio:1;
8761 		uint64_t nand:1;
8762 		uint64_t mii1:1;
8763 		uint64_t reserved_10_17:8;
8764 		uint64_t wdog:10;
8765 #else
8766 		uint64_t wdog:10;
8767 		uint64_t reserved_10_17:8;
8768 		uint64_t mii1:1;
8769 		uint64_t nand:1;
8770 		uint64_t mio:1;
8771 		uint64_t iob:1;
8772 		uint64_t fpa:1;
8773 		uint64_t pow:1;
8774 		uint64_t l2c:1;
8775 		uint64_t ipd:1;
8776 		uint64_t pip:1;
8777 		uint64_t pko:1;
8778 		uint64_t zip:1;
8779 		uint64_t tim:1;
8780 		uint64_t rad:1;
8781 		uint64_t key:1;
8782 		uint64_t dfa:1;
8783 		uint64_t usb:1;
8784 		uint64_t sli:1;
8785 		uint64_t dpi:1;
8786 		uint64_t agx0:1;
8787 		uint64_t agx1:1;
8788 		uint64_t reserved_38_45:8;
8789 		uint64_t agl:1;
8790 		uint64_t ptp:1;
8791 		uint64_t pem0:1;
8792 		uint64_t pem1:1;
8793 		uint64_t srio0:1;
8794 		uint64_t reserved_51_51:1;
8795 		uint64_t lmc0:1;
8796 		uint64_t reserved_53_55:3;
8797 		uint64_t dfm:1;
8798 		uint64_t reserved_57_59:3;
8799 		uint64_t srio2:1;
8800 		uint64_t srio3:1;
8801 		uint64_t reserved_62_62:1;
8802 		uint64_t rst:1;
8803 #endif
8804 	} cn66xx;
8805 	struct cvmx_ciu_sum1_iox_int_cnf71xx {
8806 #ifdef __BIG_ENDIAN_BITFIELD
8807 		uint64_t rst:1;
8808 		uint64_t reserved_53_62:10;
8809 		uint64_t lmc0:1;
8810 		uint64_t reserved_50_51:2;
8811 		uint64_t pem1:1;
8812 		uint64_t pem0:1;
8813 		uint64_t ptp:1;
8814 		uint64_t reserved_41_46:6;
8815 		uint64_t dpi_dma:1;
8816 		uint64_t reserved_37_39:3;
8817 		uint64_t agx0:1;
8818 		uint64_t dpi:1;
8819 		uint64_t sli:1;
8820 		uint64_t usb:1;
8821 		uint64_t reserved_32_32:1;
8822 		uint64_t key:1;
8823 		uint64_t rad:1;
8824 		uint64_t tim:1;
8825 		uint64_t reserved_28_28:1;
8826 		uint64_t pko:1;
8827 		uint64_t pip:1;
8828 		uint64_t ipd:1;
8829 		uint64_t l2c:1;
8830 		uint64_t pow:1;
8831 		uint64_t fpa:1;
8832 		uint64_t iob:1;
8833 		uint64_t mio:1;
8834 		uint64_t nand:1;
8835 		uint64_t reserved_4_18:15;
8836 		uint64_t wdog:4;
8837 #else
8838 		uint64_t wdog:4;
8839 		uint64_t reserved_4_18:15;
8840 		uint64_t nand:1;
8841 		uint64_t mio:1;
8842 		uint64_t iob:1;
8843 		uint64_t fpa:1;
8844 		uint64_t pow:1;
8845 		uint64_t l2c:1;
8846 		uint64_t ipd:1;
8847 		uint64_t pip:1;
8848 		uint64_t pko:1;
8849 		uint64_t reserved_28_28:1;
8850 		uint64_t tim:1;
8851 		uint64_t rad:1;
8852 		uint64_t key:1;
8853 		uint64_t reserved_32_32:1;
8854 		uint64_t usb:1;
8855 		uint64_t sli:1;
8856 		uint64_t dpi:1;
8857 		uint64_t agx0:1;
8858 		uint64_t reserved_37_39:3;
8859 		uint64_t dpi_dma:1;
8860 		uint64_t reserved_41_46:6;
8861 		uint64_t ptp:1;
8862 		uint64_t pem0:1;
8863 		uint64_t pem1:1;
8864 		uint64_t reserved_50_51:2;
8865 		uint64_t lmc0:1;
8866 		uint64_t reserved_53_62:10;
8867 		uint64_t rst:1;
8868 #endif
8869 	} cnf71xx;
8870 };
8871 
8872 union cvmx_ciu_sum1_ppx_ip2 {
8873 	uint64_t u64;
8874 	struct cvmx_ciu_sum1_ppx_ip2_s {
8875 #ifdef __BIG_ENDIAN_BITFIELD
8876 		uint64_t rst:1;
8877 		uint64_t reserved_62_62:1;
8878 		uint64_t srio3:1;
8879 		uint64_t srio2:1;
8880 		uint64_t reserved_57_59:3;
8881 		uint64_t dfm:1;
8882 		uint64_t reserved_53_55:3;
8883 		uint64_t lmc0:1;
8884 		uint64_t reserved_51_51:1;
8885 		uint64_t srio0:1;
8886 		uint64_t pem1:1;
8887 		uint64_t pem0:1;
8888 		uint64_t ptp:1;
8889 		uint64_t agl:1;
8890 		uint64_t reserved_41_45:5;
8891 		uint64_t dpi_dma:1;
8892 		uint64_t reserved_38_39:2;
8893 		uint64_t agx1:1;
8894 		uint64_t agx0:1;
8895 		uint64_t dpi:1;
8896 		uint64_t sli:1;
8897 		uint64_t usb:1;
8898 		uint64_t dfa:1;
8899 		uint64_t key:1;
8900 		uint64_t rad:1;
8901 		uint64_t tim:1;
8902 		uint64_t zip:1;
8903 		uint64_t pko:1;
8904 		uint64_t pip:1;
8905 		uint64_t ipd:1;
8906 		uint64_t l2c:1;
8907 		uint64_t pow:1;
8908 		uint64_t fpa:1;
8909 		uint64_t iob:1;
8910 		uint64_t mio:1;
8911 		uint64_t nand:1;
8912 		uint64_t mii1:1;
8913 		uint64_t reserved_10_17:8;
8914 		uint64_t wdog:10;
8915 #else
8916 		uint64_t wdog:10;
8917 		uint64_t reserved_10_17:8;
8918 		uint64_t mii1:1;
8919 		uint64_t nand:1;
8920 		uint64_t mio:1;
8921 		uint64_t iob:1;
8922 		uint64_t fpa:1;
8923 		uint64_t pow:1;
8924 		uint64_t l2c:1;
8925 		uint64_t ipd:1;
8926 		uint64_t pip:1;
8927 		uint64_t pko:1;
8928 		uint64_t zip:1;
8929 		uint64_t tim:1;
8930 		uint64_t rad:1;
8931 		uint64_t key:1;
8932 		uint64_t dfa:1;
8933 		uint64_t usb:1;
8934 		uint64_t sli:1;
8935 		uint64_t dpi:1;
8936 		uint64_t agx0:1;
8937 		uint64_t agx1:1;
8938 		uint64_t reserved_38_39:2;
8939 		uint64_t dpi_dma:1;
8940 		uint64_t reserved_41_45:5;
8941 		uint64_t agl:1;
8942 		uint64_t ptp:1;
8943 		uint64_t pem0:1;
8944 		uint64_t pem1:1;
8945 		uint64_t srio0:1;
8946 		uint64_t reserved_51_51:1;
8947 		uint64_t lmc0:1;
8948 		uint64_t reserved_53_55:3;
8949 		uint64_t dfm:1;
8950 		uint64_t reserved_57_59:3;
8951 		uint64_t srio2:1;
8952 		uint64_t srio3:1;
8953 		uint64_t reserved_62_62:1;
8954 		uint64_t rst:1;
8955 #endif
8956 	} s;
8957 	struct cvmx_ciu_sum1_ppx_ip2_cn61xx {
8958 #ifdef __BIG_ENDIAN_BITFIELD
8959 		uint64_t rst:1;
8960 		uint64_t reserved_53_62:10;
8961 		uint64_t lmc0:1;
8962 		uint64_t reserved_50_51:2;
8963 		uint64_t pem1:1;
8964 		uint64_t pem0:1;
8965 		uint64_t ptp:1;
8966 		uint64_t agl:1;
8967 		uint64_t reserved_41_45:5;
8968 		uint64_t dpi_dma:1;
8969 		uint64_t reserved_38_39:2;
8970 		uint64_t agx1:1;
8971 		uint64_t agx0:1;
8972 		uint64_t dpi:1;
8973 		uint64_t sli:1;
8974 		uint64_t usb:1;
8975 		uint64_t dfa:1;
8976 		uint64_t key:1;
8977 		uint64_t rad:1;
8978 		uint64_t tim:1;
8979 		uint64_t zip:1;
8980 		uint64_t pko:1;
8981 		uint64_t pip:1;
8982 		uint64_t ipd:1;
8983 		uint64_t l2c:1;
8984 		uint64_t pow:1;
8985 		uint64_t fpa:1;
8986 		uint64_t iob:1;
8987 		uint64_t mio:1;
8988 		uint64_t nand:1;
8989 		uint64_t mii1:1;
8990 		uint64_t reserved_4_17:14;
8991 		uint64_t wdog:4;
8992 #else
8993 		uint64_t wdog:4;
8994 		uint64_t reserved_4_17:14;
8995 		uint64_t mii1:1;
8996 		uint64_t nand:1;
8997 		uint64_t mio:1;
8998 		uint64_t iob:1;
8999 		uint64_t fpa:1;
9000 		uint64_t pow:1;
9001 		uint64_t l2c:1;
9002 		uint64_t ipd:1;
9003 		uint64_t pip:1;
9004 		uint64_t pko:1;
9005 		uint64_t zip:1;
9006 		uint64_t tim:1;
9007 		uint64_t rad:1;
9008 		uint64_t key:1;
9009 		uint64_t dfa:1;
9010 		uint64_t usb:1;
9011 		uint64_t sli:1;
9012 		uint64_t dpi:1;
9013 		uint64_t agx0:1;
9014 		uint64_t agx1:1;
9015 		uint64_t reserved_38_39:2;
9016 		uint64_t dpi_dma:1;
9017 		uint64_t reserved_41_45:5;
9018 		uint64_t agl:1;
9019 		uint64_t ptp:1;
9020 		uint64_t pem0:1;
9021 		uint64_t pem1:1;
9022 		uint64_t reserved_50_51:2;
9023 		uint64_t lmc0:1;
9024 		uint64_t reserved_53_62:10;
9025 		uint64_t rst:1;
9026 #endif
9027 	} cn61xx;
9028 	struct cvmx_ciu_sum1_ppx_ip2_cn66xx {
9029 #ifdef __BIG_ENDIAN_BITFIELD
9030 		uint64_t rst:1;
9031 		uint64_t reserved_62_62:1;
9032 		uint64_t srio3:1;
9033 		uint64_t srio2:1;
9034 		uint64_t reserved_57_59:3;
9035 		uint64_t dfm:1;
9036 		uint64_t reserved_53_55:3;
9037 		uint64_t lmc0:1;
9038 		uint64_t reserved_51_51:1;
9039 		uint64_t srio0:1;
9040 		uint64_t pem1:1;
9041 		uint64_t pem0:1;
9042 		uint64_t ptp:1;
9043 		uint64_t agl:1;
9044 		uint64_t reserved_38_45:8;
9045 		uint64_t agx1:1;
9046 		uint64_t agx0:1;
9047 		uint64_t dpi:1;
9048 		uint64_t sli:1;
9049 		uint64_t usb:1;
9050 		uint64_t dfa:1;
9051 		uint64_t key:1;
9052 		uint64_t rad:1;
9053 		uint64_t tim:1;
9054 		uint64_t zip:1;
9055 		uint64_t pko:1;
9056 		uint64_t pip:1;
9057 		uint64_t ipd:1;
9058 		uint64_t l2c:1;
9059 		uint64_t pow:1;
9060 		uint64_t fpa:1;
9061 		uint64_t iob:1;
9062 		uint64_t mio:1;
9063 		uint64_t nand:1;
9064 		uint64_t mii1:1;
9065 		uint64_t reserved_10_17:8;
9066 		uint64_t wdog:10;
9067 #else
9068 		uint64_t wdog:10;
9069 		uint64_t reserved_10_17:8;
9070 		uint64_t mii1:1;
9071 		uint64_t nand:1;
9072 		uint64_t mio:1;
9073 		uint64_t iob:1;
9074 		uint64_t fpa:1;
9075 		uint64_t pow:1;
9076 		uint64_t l2c:1;
9077 		uint64_t ipd:1;
9078 		uint64_t pip:1;
9079 		uint64_t pko:1;
9080 		uint64_t zip:1;
9081 		uint64_t tim:1;
9082 		uint64_t rad:1;
9083 		uint64_t key:1;
9084 		uint64_t dfa:1;
9085 		uint64_t usb:1;
9086 		uint64_t sli:1;
9087 		uint64_t dpi:1;
9088 		uint64_t agx0:1;
9089 		uint64_t agx1:1;
9090 		uint64_t reserved_38_45:8;
9091 		uint64_t agl:1;
9092 		uint64_t ptp:1;
9093 		uint64_t pem0:1;
9094 		uint64_t pem1:1;
9095 		uint64_t srio0:1;
9096 		uint64_t reserved_51_51:1;
9097 		uint64_t lmc0:1;
9098 		uint64_t reserved_53_55:3;
9099 		uint64_t dfm:1;
9100 		uint64_t reserved_57_59:3;
9101 		uint64_t srio2:1;
9102 		uint64_t srio3:1;
9103 		uint64_t reserved_62_62:1;
9104 		uint64_t rst:1;
9105 #endif
9106 	} cn66xx;
9107 	struct cvmx_ciu_sum1_ppx_ip2_cnf71xx {
9108 #ifdef __BIG_ENDIAN_BITFIELD
9109 		uint64_t rst:1;
9110 		uint64_t reserved_53_62:10;
9111 		uint64_t lmc0:1;
9112 		uint64_t reserved_50_51:2;
9113 		uint64_t pem1:1;
9114 		uint64_t pem0:1;
9115 		uint64_t ptp:1;
9116 		uint64_t reserved_41_46:6;
9117 		uint64_t dpi_dma:1;
9118 		uint64_t reserved_37_39:3;
9119 		uint64_t agx0:1;
9120 		uint64_t dpi:1;
9121 		uint64_t sli:1;
9122 		uint64_t usb:1;
9123 		uint64_t reserved_32_32:1;
9124 		uint64_t key:1;
9125 		uint64_t rad:1;
9126 		uint64_t tim:1;
9127 		uint64_t reserved_28_28:1;
9128 		uint64_t pko:1;
9129 		uint64_t pip:1;
9130 		uint64_t ipd:1;
9131 		uint64_t l2c:1;
9132 		uint64_t pow:1;
9133 		uint64_t fpa:1;
9134 		uint64_t iob:1;
9135 		uint64_t mio:1;
9136 		uint64_t nand:1;
9137 		uint64_t reserved_4_18:15;
9138 		uint64_t wdog:4;
9139 #else
9140 		uint64_t wdog:4;
9141 		uint64_t reserved_4_18:15;
9142 		uint64_t nand:1;
9143 		uint64_t mio:1;
9144 		uint64_t iob:1;
9145 		uint64_t fpa:1;
9146 		uint64_t pow:1;
9147 		uint64_t l2c:1;
9148 		uint64_t ipd:1;
9149 		uint64_t pip:1;
9150 		uint64_t pko:1;
9151 		uint64_t reserved_28_28:1;
9152 		uint64_t tim:1;
9153 		uint64_t rad:1;
9154 		uint64_t key:1;
9155 		uint64_t reserved_32_32:1;
9156 		uint64_t usb:1;
9157 		uint64_t sli:1;
9158 		uint64_t dpi:1;
9159 		uint64_t agx0:1;
9160 		uint64_t reserved_37_39:3;
9161 		uint64_t dpi_dma:1;
9162 		uint64_t reserved_41_46:6;
9163 		uint64_t ptp:1;
9164 		uint64_t pem0:1;
9165 		uint64_t pem1:1;
9166 		uint64_t reserved_50_51:2;
9167 		uint64_t lmc0:1;
9168 		uint64_t reserved_53_62:10;
9169 		uint64_t rst:1;
9170 #endif
9171 	} cnf71xx;
9172 };
9173 
9174 union cvmx_ciu_sum1_ppx_ip3 {
9175 	uint64_t u64;
9176 	struct cvmx_ciu_sum1_ppx_ip3_s {
9177 #ifdef __BIG_ENDIAN_BITFIELD
9178 		uint64_t rst:1;
9179 		uint64_t reserved_62_62:1;
9180 		uint64_t srio3:1;
9181 		uint64_t srio2:1;
9182 		uint64_t reserved_57_59:3;
9183 		uint64_t dfm:1;
9184 		uint64_t reserved_53_55:3;
9185 		uint64_t lmc0:1;
9186 		uint64_t reserved_51_51:1;
9187 		uint64_t srio0:1;
9188 		uint64_t pem1:1;
9189 		uint64_t pem0:1;
9190 		uint64_t ptp:1;
9191 		uint64_t agl:1;
9192 		uint64_t reserved_41_45:5;
9193 		uint64_t dpi_dma:1;
9194 		uint64_t reserved_38_39:2;
9195 		uint64_t agx1:1;
9196 		uint64_t agx0:1;
9197 		uint64_t dpi:1;
9198 		uint64_t sli:1;
9199 		uint64_t usb:1;
9200 		uint64_t dfa:1;
9201 		uint64_t key:1;
9202 		uint64_t rad:1;
9203 		uint64_t tim:1;
9204 		uint64_t zip:1;
9205 		uint64_t pko:1;
9206 		uint64_t pip:1;
9207 		uint64_t ipd:1;
9208 		uint64_t l2c:1;
9209 		uint64_t pow:1;
9210 		uint64_t fpa:1;
9211 		uint64_t iob:1;
9212 		uint64_t mio:1;
9213 		uint64_t nand:1;
9214 		uint64_t mii1:1;
9215 		uint64_t reserved_10_17:8;
9216 		uint64_t wdog:10;
9217 #else
9218 		uint64_t wdog:10;
9219 		uint64_t reserved_10_17:8;
9220 		uint64_t mii1:1;
9221 		uint64_t nand:1;
9222 		uint64_t mio:1;
9223 		uint64_t iob:1;
9224 		uint64_t fpa:1;
9225 		uint64_t pow:1;
9226 		uint64_t l2c:1;
9227 		uint64_t ipd:1;
9228 		uint64_t pip:1;
9229 		uint64_t pko:1;
9230 		uint64_t zip:1;
9231 		uint64_t tim:1;
9232 		uint64_t rad:1;
9233 		uint64_t key:1;
9234 		uint64_t dfa:1;
9235 		uint64_t usb:1;
9236 		uint64_t sli:1;
9237 		uint64_t dpi:1;
9238 		uint64_t agx0:1;
9239 		uint64_t agx1:1;
9240 		uint64_t reserved_38_39:2;
9241 		uint64_t dpi_dma:1;
9242 		uint64_t reserved_41_45:5;
9243 		uint64_t agl:1;
9244 		uint64_t ptp:1;
9245 		uint64_t pem0:1;
9246 		uint64_t pem1:1;
9247 		uint64_t srio0:1;
9248 		uint64_t reserved_51_51:1;
9249 		uint64_t lmc0:1;
9250 		uint64_t reserved_53_55:3;
9251 		uint64_t dfm:1;
9252 		uint64_t reserved_57_59:3;
9253 		uint64_t srio2:1;
9254 		uint64_t srio3:1;
9255 		uint64_t reserved_62_62:1;
9256 		uint64_t rst:1;
9257 #endif
9258 	} s;
9259 	struct cvmx_ciu_sum1_ppx_ip3_cn61xx {
9260 #ifdef __BIG_ENDIAN_BITFIELD
9261 		uint64_t rst:1;
9262 		uint64_t reserved_53_62:10;
9263 		uint64_t lmc0:1;
9264 		uint64_t reserved_50_51:2;
9265 		uint64_t pem1:1;
9266 		uint64_t pem0:1;
9267 		uint64_t ptp:1;
9268 		uint64_t agl:1;
9269 		uint64_t reserved_41_45:5;
9270 		uint64_t dpi_dma:1;
9271 		uint64_t reserved_38_39:2;
9272 		uint64_t agx1:1;
9273 		uint64_t agx0:1;
9274 		uint64_t dpi:1;
9275 		uint64_t sli:1;
9276 		uint64_t usb:1;
9277 		uint64_t dfa:1;
9278 		uint64_t key:1;
9279 		uint64_t rad:1;
9280 		uint64_t tim:1;
9281 		uint64_t zip:1;
9282 		uint64_t pko:1;
9283 		uint64_t pip:1;
9284 		uint64_t ipd:1;
9285 		uint64_t l2c:1;
9286 		uint64_t pow:1;
9287 		uint64_t fpa:1;
9288 		uint64_t iob:1;
9289 		uint64_t mio:1;
9290 		uint64_t nand:1;
9291 		uint64_t mii1:1;
9292 		uint64_t reserved_4_17:14;
9293 		uint64_t wdog:4;
9294 #else
9295 		uint64_t wdog:4;
9296 		uint64_t reserved_4_17:14;
9297 		uint64_t mii1:1;
9298 		uint64_t nand:1;
9299 		uint64_t mio:1;
9300 		uint64_t iob:1;
9301 		uint64_t fpa:1;
9302 		uint64_t pow:1;
9303 		uint64_t l2c:1;
9304 		uint64_t ipd:1;
9305 		uint64_t pip:1;
9306 		uint64_t pko:1;
9307 		uint64_t zip:1;
9308 		uint64_t tim:1;
9309 		uint64_t rad:1;
9310 		uint64_t key:1;
9311 		uint64_t dfa:1;
9312 		uint64_t usb:1;
9313 		uint64_t sli:1;
9314 		uint64_t dpi:1;
9315 		uint64_t agx0:1;
9316 		uint64_t agx1:1;
9317 		uint64_t reserved_38_39:2;
9318 		uint64_t dpi_dma:1;
9319 		uint64_t reserved_41_45:5;
9320 		uint64_t agl:1;
9321 		uint64_t ptp:1;
9322 		uint64_t pem0:1;
9323 		uint64_t pem1:1;
9324 		uint64_t reserved_50_51:2;
9325 		uint64_t lmc0:1;
9326 		uint64_t reserved_53_62:10;
9327 		uint64_t rst:1;
9328 #endif
9329 	} cn61xx;
9330 	struct cvmx_ciu_sum1_ppx_ip3_cn66xx {
9331 #ifdef __BIG_ENDIAN_BITFIELD
9332 		uint64_t rst:1;
9333 		uint64_t reserved_62_62:1;
9334 		uint64_t srio3:1;
9335 		uint64_t srio2:1;
9336 		uint64_t reserved_57_59:3;
9337 		uint64_t dfm:1;
9338 		uint64_t reserved_53_55:3;
9339 		uint64_t lmc0:1;
9340 		uint64_t reserved_51_51:1;
9341 		uint64_t srio0:1;
9342 		uint64_t pem1:1;
9343 		uint64_t pem0:1;
9344 		uint64_t ptp:1;
9345 		uint64_t agl:1;
9346 		uint64_t reserved_38_45:8;
9347 		uint64_t agx1:1;
9348 		uint64_t agx0:1;
9349 		uint64_t dpi:1;
9350 		uint64_t sli:1;
9351 		uint64_t usb:1;
9352 		uint64_t dfa:1;
9353 		uint64_t key:1;
9354 		uint64_t rad:1;
9355 		uint64_t tim:1;
9356 		uint64_t zip:1;
9357 		uint64_t pko:1;
9358 		uint64_t pip:1;
9359 		uint64_t ipd:1;
9360 		uint64_t l2c:1;
9361 		uint64_t pow:1;
9362 		uint64_t fpa:1;
9363 		uint64_t iob:1;
9364 		uint64_t mio:1;
9365 		uint64_t nand:1;
9366 		uint64_t mii1:1;
9367 		uint64_t reserved_10_17:8;
9368 		uint64_t wdog:10;
9369 #else
9370 		uint64_t wdog:10;
9371 		uint64_t reserved_10_17:8;
9372 		uint64_t mii1:1;
9373 		uint64_t nand:1;
9374 		uint64_t mio:1;
9375 		uint64_t iob:1;
9376 		uint64_t fpa:1;
9377 		uint64_t pow:1;
9378 		uint64_t l2c:1;
9379 		uint64_t ipd:1;
9380 		uint64_t pip:1;
9381 		uint64_t pko:1;
9382 		uint64_t zip:1;
9383 		uint64_t tim:1;
9384 		uint64_t rad:1;
9385 		uint64_t key:1;
9386 		uint64_t dfa:1;
9387 		uint64_t usb:1;
9388 		uint64_t sli:1;
9389 		uint64_t dpi:1;
9390 		uint64_t agx0:1;
9391 		uint64_t agx1:1;
9392 		uint64_t reserved_38_45:8;
9393 		uint64_t agl:1;
9394 		uint64_t ptp:1;
9395 		uint64_t pem0:1;
9396 		uint64_t pem1:1;
9397 		uint64_t srio0:1;
9398 		uint64_t reserved_51_51:1;
9399 		uint64_t lmc0:1;
9400 		uint64_t reserved_53_55:3;
9401 		uint64_t dfm:1;
9402 		uint64_t reserved_57_59:3;
9403 		uint64_t srio2:1;
9404 		uint64_t srio3:1;
9405 		uint64_t reserved_62_62:1;
9406 		uint64_t rst:1;
9407 #endif
9408 	} cn66xx;
9409 	struct cvmx_ciu_sum1_ppx_ip3_cnf71xx {
9410 #ifdef __BIG_ENDIAN_BITFIELD
9411 		uint64_t rst:1;
9412 		uint64_t reserved_53_62:10;
9413 		uint64_t lmc0:1;
9414 		uint64_t reserved_50_51:2;
9415 		uint64_t pem1:1;
9416 		uint64_t pem0:1;
9417 		uint64_t ptp:1;
9418 		uint64_t reserved_41_46:6;
9419 		uint64_t dpi_dma:1;
9420 		uint64_t reserved_37_39:3;
9421 		uint64_t agx0:1;
9422 		uint64_t dpi:1;
9423 		uint64_t sli:1;
9424 		uint64_t usb:1;
9425 		uint64_t reserved_32_32:1;
9426 		uint64_t key:1;
9427 		uint64_t rad:1;
9428 		uint64_t tim:1;
9429 		uint64_t reserved_28_28:1;
9430 		uint64_t pko:1;
9431 		uint64_t pip:1;
9432 		uint64_t ipd:1;
9433 		uint64_t l2c:1;
9434 		uint64_t pow:1;
9435 		uint64_t fpa:1;
9436 		uint64_t iob:1;
9437 		uint64_t mio:1;
9438 		uint64_t nand:1;
9439 		uint64_t reserved_4_18:15;
9440 		uint64_t wdog:4;
9441 #else
9442 		uint64_t wdog:4;
9443 		uint64_t reserved_4_18:15;
9444 		uint64_t nand:1;
9445 		uint64_t mio:1;
9446 		uint64_t iob:1;
9447 		uint64_t fpa:1;
9448 		uint64_t pow:1;
9449 		uint64_t l2c:1;
9450 		uint64_t ipd:1;
9451 		uint64_t pip:1;
9452 		uint64_t pko:1;
9453 		uint64_t reserved_28_28:1;
9454 		uint64_t tim:1;
9455 		uint64_t rad:1;
9456 		uint64_t key:1;
9457 		uint64_t reserved_32_32:1;
9458 		uint64_t usb:1;
9459 		uint64_t sli:1;
9460 		uint64_t dpi:1;
9461 		uint64_t agx0:1;
9462 		uint64_t reserved_37_39:3;
9463 		uint64_t dpi_dma:1;
9464 		uint64_t reserved_41_46:6;
9465 		uint64_t ptp:1;
9466 		uint64_t pem0:1;
9467 		uint64_t pem1:1;
9468 		uint64_t reserved_50_51:2;
9469 		uint64_t lmc0:1;
9470 		uint64_t reserved_53_62:10;
9471 		uint64_t rst:1;
9472 #endif
9473 	} cnf71xx;
9474 };
9475 
9476 union cvmx_ciu_sum1_ppx_ip4 {
9477 	uint64_t u64;
9478 	struct cvmx_ciu_sum1_ppx_ip4_s {
9479 #ifdef __BIG_ENDIAN_BITFIELD
9480 		uint64_t rst:1;
9481 		uint64_t reserved_62_62:1;
9482 		uint64_t srio3:1;
9483 		uint64_t srio2:1;
9484 		uint64_t reserved_57_59:3;
9485 		uint64_t dfm:1;
9486 		uint64_t reserved_53_55:3;
9487 		uint64_t lmc0:1;
9488 		uint64_t reserved_51_51:1;
9489 		uint64_t srio0:1;
9490 		uint64_t pem1:1;
9491 		uint64_t pem0:1;
9492 		uint64_t ptp:1;
9493 		uint64_t agl:1;
9494 		uint64_t reserved_41_45:5;
9495 		uint64_t dpi_dma:1;
9496 		uint64_t reserved_38_39:2;
9497 		uint64_t agx1:1;
9498 		uint64_t agx0:1;
9499 		uint64_t dpi:1;
9500 		uint64_t sli:1;
9501 		uint64_t usb:1;
9502 		uint64_t dfa:1;
9503 		uint64_t key:1;
9504 		uint64_t rad:1;
9505 		uint64_t tim:1;
9506 		uint64_t zip:1;
9507 		uint64_t pko:1;
9508 		uint64_t pip:1;
9509 		uint64_t ipd:1;
9510 		uint64_t l2c:1;
9511 		uint64_t pow:1;
9512 		uint64_t fpa:1;
9513 		uint64_t iob:1;
9514 		uint64_t mio:1;
9515 		uint64_t nand:1;
9516 		uint64_t mii1:1;
9517 		uint64_t reserved_10_17:8;
9518 		uint64_t wdog:10;
9519 #else
9520 		uint64_t wdog:10;
9521 		uint64_t reserved_10_17:8;
9522 		uint64_t mii1:1;
9523 		uint64_t nand:1;
9524 		uint64_t mio:1;
9525 		uint64_t iob:1;
9526 		uint64_t fpa:1;
9527 		uint64_t pow:1;
9528 		uint64_t l2c:1;
9529 		uint64_t ipd:1;
9530 		uint64_t pip:1;
9531 		uint64_t pko:1;
9532 		uint64_t zip:1;
9533 		uint64_t tim:1;
9534 		uint64_t rad:1;
9535 		uint64_t key:1;
9536 		uint64_t dfa:1;
9537 		uint64_t usb:1;
9538 		uint64_t sli:1;
9539 		uint64_t dpi:1;
9540 		uint64_t agx0:1;
9541 		uint64_t agx1:1;
9542 		uint64_t reserved_38_39:2;
9543 		uint64_t dpi_dma:1;
9544 		uint64_t reserved_41_45:5;
9545 		uint64_t agl:1;
9546 		uint64_t ptp:1;
9547 		uint64_t pem0:1;
9548 		uint64_t pem1:1;
9549 		uint64_t srio0:1;
9550 		uint64_t reserved_51_51:1;
9551 		uint64_t lmc0:1;
9552 		uint64_t reserved_53_55:3;
9553 		uint64_t dfm:1;
9554 		uint64_t reserved_57_59:3;
9555 		uint64_t srio2:1;
9556 		uint64_t srio3:1;
9557 		uint64_t reserved_62_62:1;
9558 		uint64_t rst:1;
9559 #endif
9560 	} s;
9561 	struct cvmx_ciu_sum1_ppx_ip4_cn61xx {
9562 #ifdef __BIG_ENDIAN_BITFIELD
9563 		uint64_t rst:1;
9564 		uint64_t reserved_53_62:10;
9565 		uint64_t lmc0:1;
9566 		uint64_t reserved_50_51:2;
9567 		uint64_t pem1:1;
9568 		uint64_t pem0:1;
9569 		uint64_t ptp:1;
9570 		uint64_t agl:1;
9571 		uint64_t reserved_41_45:5;
9572 		uint64_t dpi_dma:1;
9573 		uint64_t reserved_38_39:2;
9574 		uint64_t agx1:1;
9575 		uint64_t agx0:1;
9576 		uint64_t dpi:1;
9577 		uint64_t sli:1;
9578 		uint64_t usb:1;
9579 		uint64_t dfa:1;
9580 		uint64_t key:1;
9581 		uint64_t rad:1;
9582 		uint64_t tim:1;
9583 		uint64_t zip:1;
9584 		uint64_t pko:1;
9585 		uint64_t pip:1;
9586 		uint64_t ipd:1;
9587 		uint64_t l2c:1;
9588 		uint64_t pow:1;
9589 		uint64_t fpa:1;
9590 		uint64_t iob:1;
9591 		uint64_t mio:1;
9592 		uint64_t nand:1;
9593 		uint64_t mii1:1;
9594 		uint64_t reserved_4_17:14;
9595 		uint64_t wdog:4;
9596 #else
9597 		uint64_t wdog:4;
9598 		uint64_t reserved_4_17:14;
9599 		uint64_t mii1:1;
9600 		uint64_t nand:1;
9601 		uint64_t mio:1;
9602 		uint64_t iob:1;
9603 		uint64_t fpa:1;
9604 		uint64_t pow:1;
9605 		uint64_t l2c:1;
9606 		uint64_t ipd:1;
9607 		uint64_t pip:1;
9608 		uint64_t pko:1;
9609 		uint64_t zip:1;
9610 		uint64_t tim:1;
9611 		uint64_t rad:1;
9612 		uint64_t key:1;
9613 		uint64_t dfa:1;
9614 		uint64_t usb:1;
9615 		uint64_t sli:1;
9616 		uint64_t dpi:1;
9617 		uint64_t agx0:1;
9618 		uint64_t agx1:1;
9619 		uint64_t reserved_38_39:2;
9620 		uint64_t dpi_dma:1;
9621 		uint64_t reserved_41_45:5;
9622 		uint64_t agl:1;
9623 		uint64_t ptp:1;
9624 		uint64_t pem0:1;
9625 		uint64_t pem1:1;
9626 		uint64_t reserved_50_51:2;
9627 		uint64_t lmc0:1;
9628 		uint64_t reserved_53_62:10;
9629 		uint64_t rst:1;
9630 #endif
9631 	} cn61xx;
9632 	struct cvmx_ciu_sum1_ppx_ip4_cn66xx {
9633 #ifdef __BIG_ENDIAN_BITFIELD
9634 		uint64_t rst:1;
9635 		uint64_t reserved_62_62:1;
9636 		uint64_t srio3:1;
9637 		uint64_t srio2:1;
9638 		uint64_t reserved_57_59:3;
9639 		uint64_t dfm:1;
9640 		uint64_t reserved_53_55:3;
9641 		uint64_t lmc0:1;
9642 		uint64_t reserved_51_51:1;
9643 		uint64_t srio0:1;
9644 		uint64_t pem1:1;
9645 		uint64_t pem0:1;
9646 		uint64_t ptp:1;
9647 		uint64_t agl:1;
9648 		uint64_t reserved_38_45:8;
9649 		uint64_t agx1:1;
9650 		uint64_t agx0:1;
9651 		uint64_t dpi:1;
9652 		uint64_t sli:1;
9653 		uint64_t usb:1;
9654 		uint64_t dfa:1;
9655 		uint64_t key:1;
9656 		uint64_t rad:1;
9657 		uint64_t tim:1;
9658 		uint64_t zip:1;
9659 		uint64_t pko:1;
9660 		uint64_t pip:1;
9661 		uint64_t ipd:1;
9662 		uint64_t l2c:1;
9663 		uint64_t pow:1;
9664 		uint64_t fpa:1;
9665 		uint64_t iob:1;
9666 		uint64_t mio:1;
9667 		uint64_t nand:1;
9668 		uint64_t mii1:1;
9669 		uint64_t reserved_10_17:8;
9670 		uint64_t wdog:10;
9671 #else
9672 		uint64_t wdog:10;
9673 		uint64_t reserved_10_17:8;
9674 		uint64_t mii1:1;
9675 		uint64_t nand:1;
9676 		uint64_t mio:1;
9677 		uint64_t iob:1;
9678 		uint64_t fpa:1;
9679 		uint64_t pow:1;
9680 		uint64_t l2c:1;
9681 		uint64_t ipd:1;
9682 		uint64_t pip:1;
9683 		uint64_t pko:1;
9684 		uint64_t zip:1;
9685 		uint64_t tim:1;
9686 		uint64_t rad:1;
9687 		uint64_t key:1;
9688 		uint64_t dfa:1;
9689 		uint64_t usb:1;
9690 		uint64_t sli:1;
9691 		uint64_t dpi:1;
9692 		uint64_t agx0:1;
9693 		uint64_t agx1:1;
9694 		uint64_t reserved_38_45:8;
9695 		uint64_t agl:1;
9696 		uint64_t ptp:1;
9697 		uint64_t pem0:1;
9698 		uint64_t pem1:1;
9699 		uint64_t srio0:1;
9700 		uint64_t reserved_51_51:1;
9701 		uint64_t lmc0:1;
9702 		uint64_t reserved_53_55:3;
9703 		uint64_t dfm:1;
9704 		uint64_t reserved_57_59:3;
9705 		uint64_t srio2:1;
9706 		uint64_t srio3:1;
9707 		uint64_t reserved_62_62:1;
9708 		uint64_t rst:1;
9709 #endif
9710 	} cn66xx;
9711 	struct cvmx_ciu_sum1_ppx_ip4_cnf71xx {
9712 #ifdef __BIG_ENDIAN_BITFIELD
9713 		uint64_t rst:1;
9714 		uint64_t reserved_53_62:10;
9715 		uint64_t lmc0:1;
9716 		uint64_t reserved_50_51:2;
9717 		uint64_t pem1:1;
9718 		uint64_t pem0:1;
9719 		uint64_t ptp:1;
9720 		uint64_t reserved_41_46:6;
9721 		uint64_t dpi_dma:1;
9722 		uint64_t reserved_37_39:3;
9723 		uint64_t agx0:1;
9724 		uint64_t dpi:1;
9725 		uint64_t sli:1;
9726 		uint64_t usb:1;
9727 		uint64_t reserved_32_32:1;
9728 		uint64_t key:1;
9729 		uint64_t rad:1;
9730 		uint64_t tim:1;
9731 		uint64_t reserved_28_28:1;
9732 		uint64_t pko:1;
9733 		uint64_t pip:1;
9734 		uint64_t ipd:1;
9735 		uint64_t l2c:1;
9736 		uint64_t pow:1;
9737 		uint64_t fpa:1;
9738 		uint64_t iob:1;
9739 		uint64_t mio:1;
9740 		uint64_t nand:1;
9741 		uint64_t reserved_4_18:15;
9742 		uint64_t wdog:4;
9743 #else
9744 		uint64_t wdog:4;
9745 		uint64_t reserved_4_18:15;
9746 		uint64_t nand:1;
9747 		uint64_t mio:1;
9748 		uint64_t iob:1;
9749 		uint64_t fpa:1;
9750 		uint64_t pow:1;
9751 		uint64_t l2c:1;
9752 		uint64_t ipd:1;
9753 		uint64_t pip:1;
9754 		uint64_t pko:1;
9755 		uint64_t reserved_28_28:1;
9756 		uint64_t tim:1;
9757 		uint64_t rad:1;
9758 		uint64_t key:1;
9759 		uint64_t reserved_32_32:1;
9760 		uint64_t usb:1;
9761 		uint64_t sli:1;
9762 		uint64_t dpi:1;
9763 		uint64_t agx0:1;
9764 		uint64_t reserved_37_39:3;
9765 		uint64_t dpi_dma:1;
9766 		uint64_t reserved_41_46:6;
9767 		uint64_t ptp:1;
9768 		uint64_t pem0:1;
9769 		uint64_t pem1:1;
9770 		uint64_t reserved_50_51:2;
9771 		uint64_t lmc0:1;
9772 		uint64_t reserved_53_62:10;
9773 		uint64_t rst:1;
9774 #endif
9775 	} cnf71xx;
9776 };
9777 
9778 union cvmx_ciu_sum2_iox_int {
9779 	uint64_t u64;
9780 	struct cvmx_ciu_sum2_iox_int_s {
9781 #ifdef __BIG_ENDIAN_BITFIELD
9782 		uint64_t reserved_15_63:49;
9783 		uint64_t endor:2;
9784 		uint64_t eoi:1;
9785 		uint64_t reserved_10_11:2;
9786 		uint64_t timer:6;
9787 		uint64_t reserved_0_3:4;
9788 #else
9789 		uint64_t reserved_0_3:4;
9790 		uint64_t timer:6;
9791 		uint64_t reserved_10_11:2;
9792 		uint64_t eoi:1;
9793 		uint64_t endor:2;
9794 		uint64_t reserved_15_63:49;
9795 #endif
9796 	} s;
9797 	struct cvmx_ciu_sum2_iox_int_cn61xx {
9798 #ifdef __BIG_ENDIAN_BITFIELD
9799 		uint64_t reserved_10_63:54;
9800 		uint64_t timer:6;
9801 		uint64_t reserved_0_3:4;
9802 #else
9803 		uint64_t reserved_0_3:4;
9804 		uint64_t timer:6;
9805 		uint64_t reserved_10_63:54;
9806 #endif
9807 	} cn61xx;
9808 	struct cvmx_ciu_sum2_iox_int_cn61xx cn66xx;
9809 	struct cvmx_ciu_sum2_iox_int_s cnf71xx;
9810 };
9811 
9812 union cvmx_ciu_sum2_ppx_ip2 {
9813 	uint64_t u64;
9814 	struct cvmx_ciu_sum2_ppx_ip2_s {
9815 #ifdef __BIG_ENDIAN_BITFIELD
9816 		uint64_t reserved_15_63:49;
9817 		uint64_t endor:2;
9818 		uint64_t eoi:1;
9819 		uint64_t reserved_10_11:2;
9820 		uint64_t timer:6;
9821 		uint64_t reserved_0_3:4;
9822 #else
9823 		uint64_t reserved_0_3:4;
9824 		uint64_t timer:6;
9825 		uint64_t reserved_10_11:2;
9826 		uint64_t eoi:1;
9827 		uint64_t endor:2;
9828 		uint64_t reserved_15_63:49;
9829 #endif
9830 	} s;
9831 	struct cvmx_ciu_sum2_ppx_ip2_cn61xx {
9832 #ifdef __BIG_ENDIAN_BITFIELD
9833 		uint64_t reserved_10_63:54;
9834 		uint64_t timer:6;
9835 		uint64_t reserved_0_3:4;
9836 #else
9837 		uint64_t reserved_0_3:4;
9838 		uint64_t timer:6;
9839 		uint64_t reserved_10_63:54;
9840 #endif
9841 	} cn61xx;
9842 	struct cvmx_ciu_sum2_ppx_ip2_cn61xx cn66xx;
9843 	struct cvmx_ciu_sum2_ppx_ip2_s cnf71xx;
9844 };
9845 
9846 union cvmx_ciu_sum2_ppx_ip3 {
9847 	uint64_t u64;
9848 	struct cvmx_ciu_sum2_ppx_ip3_s {
9849 #ifdef __BIG_ENDIAN_BITFIELD
9850 		uint64_t reserved_15_63:49;
9851 		uint64_t endor:2;
9852 		uint64_t eoi:1;
9853 		uint64_t reserved_10_11:2;
9854 		uint64_t timer:6;
9855 		uint64_t reserved_0_3:4;
9856 #else
9857 		uint64_t reserved_0_3:4;
9858 		uint64_t timer:6;
9859 		uint64_t reserved_10_11:2;
9860 		uint64_t eoi:1;
9861 		uint64_t endor:2;
9862 		uint64_t reserved_15_63:49;
9863 #endif
9864 	} s;
9865 	struct cvmx_ciu_sum2_ppx_ip3_cn61xx {
9866 #ifdef __BIG_ENDIAN_BITFIELD
9867 		uint64_t reserved_10_63:54;
9868 		uint64_t timer:6;
9869 		uint64_t reserved_0_3:4;
9870 #else
9871 		uint64_t reserved_0_3:4;
9872 		uint64_t timer:6;
9873 		uint64_t reserved_10_63:54;
9874 #endif
9875 	} cn61xx;
9876 	struct cvmx_ciu_sum2_ppx_ip3_cn61xx cn66xx;
9877 	struct cvmx_ciu_sum2_ppx_ip3_s cnf71xx;
9878 };
9879 
9880 union cvmx_ciu_sum2_ppx_ip4 {
9881 	uint64_t u64;
9882 	struct cvmx_ciu_sum2_ppx_ip4_s {
9883 #ifdef __BIG_ENDIAN_BITFIELD
9884 		uint64_t reserved_15_63:49;
9885 		uint64_t endor:2;
9886 		uint64_t eoi:1;
9887 		uint64_t reserved_10_11:2;
9888 		uint64_t timer:6;
9889 		uint64_t reserved_0_3:4;
9890 #else
9891 		uint64_t reserved_0_3:4;
9892 		uint64_t timer:6;
9893 		uint64_t reserved_10_11:2;
9894 		uint64_t eoi:1;
9895 		uint64_t endor:2;
9896 		uint64_t reserved_15_63:49;
9897 #endif
9898 	} s;
9899 	struct cvmx_ciu_sum2_ppx_ip4_cn61xx {
9900 #ifdef __BIG_ENDIAN_BITFIELD
9901 		uint64_t reserved_10_63:54;
9902 		uint64_t timer:6;
9903 		uint64_t reserved_0_3:4;
9904 #else
9905 		uint64_t reserved_0_3:4;
9906 		uint64_t timer:6;
9907 		uint64_t reserved_10_63:54;
9908 #endif
9909 	} cn61xx;
9910 	struct cvmx_ciu_sum2_ppx_ip4_cn61xx cn66xx;
9911 	struct cvmx_ciu_sum2_ppx_ip4_s cnf71xx;
9912 };
9913 
9914 union cvmx_ciu_timx {
9915 	uint64_t u64;
9916 	struct cvmx_ciu_timx_s {
9917 #ifdef __BIG_ENDIAN_BITFIELD
9918 		uint64_t reserved_37_63:27;
9919 		uint64_t one_shot:1;
9920 		uint64_t len:36;
9921 #else
9922 		uint64_t len:36;
9923 		uint64_t one_shot:1;
9924 		uint64_t reserved_37_63:27;
9925 #endif
9926 	} s;
9927 	struct cvmx_ciu_timx_s cn30xx;
9928 	struct cvmx_ciu_timx_s cn31xx;
9929 	struct cvmx_ciu_timx_s cn38xx;
9930 	struct cvmx_ciu_timx_s cn38xxp2;
9931 	struct cvmx_ciu_timx_s cn50xx;
9932 	struct cvmx_ciu_timx_s cn52xx;
9933 	struct cvmx_ciu_timx_s cn52xxp1;
9934 	struct cvmx_ciu_timx_s cn56xx;
9935 	struct cvmx_ciu_timx_s cn56xxp1;
9936 	struct cvmx_ciu_timx_s cn58xx;
9937 	struct cvmx_ciu_timx_s cn58xxp1;
9938 	struct cvmx_ciu_timx_s cn61xx;
9939 	struct cvmx_ciu_timx_s cn63xx;
9940 	struct cvmx_ciu_timx_s cn63xxp1;
9941 	struct cvmx_ciu_timx_s cn66xx;
9942 	struct cvmx_ciu_timx_s cn68xx;
9943 	struct cvmx_ciu_timx_s cn68xxp1;
9944 	struct cvmx_ciu_timx_s cnf71xx;
9945 };
9946 
9947 union cvmx_ciu_tim_multi_cast {
9948 	uint64_t u64;
9949 	struct cvmx_ciu_tim_multi_cast_s {
9950 #ifdef __BIG_ENDIAN_BITFIELD
9951 		uint64_t reserved_1_63:63;
9952 		uint64_t en:1;
9953 #else
9954 		uint64_t en:1;
9955 		uint64_t reserved_1_63:63;
9956 #endif
9957 	} s;
9958 	struct cvmx_ciu_tim_multi_cast_s cn61xx;
9959 	struct cvmx_ciu_tim_multi_cast_s cn66xx;
9960 	struct cvmx_ciu_tim_multi_cast_s cnf71xx;
9961 };
9962 
9963 union cvmx_ciu_wdogx {
9964 	uint64_t u64;
9965 	struct cvmx_ciu_wdogx_s {
9966 #ifdef __BIG_ENDIAN_BITFIELD
9967 		uint64_t reserved_46_63:18;
9968 		uint64_t gstopen:1;
9969 		uint64_t dstop:1;
9970 		uint64_t cnt:24;
9971 		uint64_t len:16;
9972 		uint64_t state:2;
9973 		uint64_t mode:2;
9974 #else
9975 		uint64_t mode:2;
9976 		uint64_t state:2;
9977 		uint64_t len:16;
9978 		uint64_t cnt:24;
9979 		uint64_t dstop:1;
9980 		uint64_t gstopen:1;
9981 		uint64_t reserved_46_63:18;
9982 #endif
9983 	} s;
9984 	struct cvmx_ciu_wdogx_s cn30xx;
9985 	struct cvmx_ciu_wdogx_s cn31xx;
9986 	struct cvmx_ciu_wdogx_s cn38xx;
9987 	struct cvmx_ciu_wdogx_s cn38xxp2;
9988 	struct cvmx_ciu_wdogx_s cn50xx;
9989 	struct cvmx_ciu_wdogx_s cn52xx;
9990 	struct cvmx_ciu_wdogx_s cn52xxp1;
9991 	struct cvmx_ciu_wdogx_s cn56xx;
9992 	struct cvmx_ciu_wdogx_s cn56xxp1;
9993 	struct cvmx_ciu_wdogx_s cn58xx;
9994 	struct cvmx_ciu_wdogx_s cn58xxp1;
9995 	struct cvmx_ciu_wdogx_s cn61xx;
9996 	struct cvmx_ciu_wdogx_s cn63xx;
9997 	struct cvmx_ciu_wdogx_s cn63xxp1;
9998 	struct cvmx_ciu_wdogx_s cn66xx;
9999 	struct cvmx_ciu_wdogx_s cn68xx;
10000 	struct cvmx_ciu_wdogx_s cn68xxp1;
10001 	struct cvmx_ciu_wdogx_s cnf71xx;
10002 };
10003 
10004 #endif
10005