/arch/mips/cavium-octeon/executive/ |
D | cvmx-helper-xaui.c | 53 gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); in __cvmx_helper_xaui_enumerate() 79 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_helper_xaui_probe() 129 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); in __cvmx_helper_xaui_enable() 137 xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface)); in __cvmx_helper_xaui_enable() 142 gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface)); in __cvmx_helper_xaui_enable() 144 gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface)); in __cvmx_helper_xaui_enable() 146 pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface)); in __cvmx_helper_xaui_enable() 152 gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); in __cvmx_helper_xaui_enable() 159 xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); in __cvmx_helper_xaui_enable() 186 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); in __cvmx_helper_xaui_enable() [all …]
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D | cvmx-l2c.c | 58 return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff; in cvmx_l2c_get_core_way_partition() 73 return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field; in cvmx_l2c_get_core_way_partition() 75 return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field; in cvmx_l2c_get_core_way_partition() 77 return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field; in cvmx_l2c_get_core_way_partition() 79 return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field; in cvmx_l2c_get_core_way_partition() 120 (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) | in cvmx_l2c_set_core_way_partition() 125 (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) | in cvmx_l2c_set_core_way_partition() 130 (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) | in cvmx_l2c_set_core_way_partition() 135 (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) | in cvmx_l2c_set_core_way_partition() 157 (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask); in cvmx_l2c_set_hw_way_partition() [all …]
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D | cvmx-helper-sgmii.c | 64 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time() 74 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time() 76 cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time() 102 cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time() 112 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time() 117 cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG in __cvmx_helper_sgmii_hardware_init_one_time() 154 cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_link() 215 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); in __cvmx_helper_sgmii_hardware_init_link_speed() 234 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); in __cvmx_helper_sgmii_hardware_init_link_speed() 241 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_link_speed() [all …]
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D | cvmx-helper-rgmii.c | 61 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_helper_rgmii_probe() 118 tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); in cvmx_helper_rgmii_internal_loopback() 120 tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); in cvmx_helper_rgmii_internal_loopback() 122 tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); in cvmx_helper_rgmii_internal_loopback() 173 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_helper_rgmii_enable() 208 cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL in __cvmx_helper_rgmii_enable() 249 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface)); in __cvmx_helper_rgmii_enable() 276 asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); in __cvmx_helper_rgmii_link_get() 321 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); in __cvmx_helper_rgmii_link_set() 326 cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & in __cvmx_helper_rgmii_link_set() [all …]
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D | cvmx-helper.c | 119 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); in __cvmx_get_mode_cn68xx() 133 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface)); in __cvmx_get_mode_cn68xx() 145 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(3)); in __cvmx_get_mode_cn68xx() 150 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1)); in __cvmx_get_mode_cn68xx() 192 mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2)); in __cvmx_get_mode_octeon2() 194 mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1)); in __cvmx_get_mode_octeon2() 211 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2)); in __cvmx_get_mode_octeon2() 219 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); in __cvmx_get_mode_octeon2() 230 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); in __cvmx_get_mode_octeon2() 240 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_get_mode_octeon2() [all …]
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D | cvmx-helper-jtag.c | 70 cvmx_read_csr(CVMX_CIU_QLM_JTGC); in cvmx_helper_qlm_jtag_init() 98 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); in cvmx_helper_qlm_jtag_shift() 142 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); in cvmx_helper_qlm_jtag_update()
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D | cvmx-spi.c | 207 spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface)); in cvmx_spi_reset_cb() 209 stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface)); in cvmx_spi_reset_cb() 219 spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface)); in cvmx_spi_reset_cb() 249 cvmx_read_csr(CVMX_SPXX_INT_REG(interface))); in cvmx_spi_reset_cb() 252 cvmx_read_csr(CVMX_STXX_INT_REG(interface))); in cvmx_spi_reset_cb() 449 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); in cvmx_spi_clock_detect_cb() 474 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); in cvmx_spi_clock_detect_cb() 533 spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface)); in cvmx_spi_training_cb() 548 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); in cvmx_spi_training_cb() 586 srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); in cvmx_spi_calendar_sync_cb() [all …]
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D | cvmx-helper-loop.c | 59 port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); in __cvmx_helper_loop_probe() 66 ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); in __cvmx_helper_loop_probe()
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D | cvmx-helper-util.c | 105 wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE); in cvmx_helper_dump_packet() 112 pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET); in cvmx_helper_dump_packet() 125 pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG); in cvmx_helper_dump_packet() 275 gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface)); in __cvmx_helper_setup_gmx() 295 gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface)); in __cvmx_helper_setup_gmx() 304 pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE); in __cvmx_helper_setup_gmx() 338 gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface)); in __cvmx_helper_setup_gmx()
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D | cvmx-cmd-queue.c | 169 status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); in cvmx_cmd_queue_initialize() 264 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); in cvmx_cmd_queue_length() 268 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); in cvmx_cmd_queue_length() 280 cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS in cvmx_cmd_queue_length()
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D | octeon-model.c | 47 while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD)) in cvmx_fuse_read_byte() 75 fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3); in octeon_model_get_string_buffer() 76 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); in octeon_model_get_string_buffer() 77 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); in octeon_model_get_string_buffer() 78 num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE)); in octeon_model_get_string_buffer()
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D | cvmx-interrupt-rsl.c | 65 csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block)); in __cvmx_interrupt_asxx_enable() 83 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_interrupt_gmxx_enable()
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D | cvmx-interrupt-decodes.c | 55 cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block))); in __cvmx_interrupt_gmxx_rxx_int_en_enable() 236 cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block))); in __cvmx_interrupt_pcsx_intx_en_reg_enable() 277 cvmx_read_csr(CVMX_PCSXX_INT_REG(index))); in __cvmx_interrupt_pcsxx_int_en_reg_enable() 307 cvmx_read_csr(CVMX_SPXX_INT_REG(index))); in __cvmx_interrupt_spxx_int_msk_enable() 346 cvmx_read_csr(CVMX_STXX_INT_REG(index))); in __cvmx_interrupt_stxx_int_msk_enable()
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D | cvmx-helper-spi.c | 89 enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE); in __cvmx_helper_spi_probe() 118 port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); in __cvmx_helper_spi_enable()
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D | cvmx-helper-npi.c | 103 cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); in __cvmx_helper_npi_enable()
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/arch/mips/include/asm/octeon/ |
D | cvmx-ipd.h | 116 ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in cvmx_ipd_config() 131 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in cvmx_ipd_enable() 150 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in cvmx_ipd_disable() 165 ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT); in cvmx_ipd_free_ptr() 170 ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in cvmx_ipd_free_ptr() 179 cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID); in cvmx_ipd_free_ptr() 196 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); in cvmx_ipd_free_ptr() 206 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); in cvmx_ipd_free_ptr() 229 cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID); in cvmx_ipd_free_ptr() 241 cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); in cvmx_ipd_free_ptr() [all …]
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D | cvmx-pip.h | 389 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num)); in cvmx_pip_get_port_status() 390 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num)); in cvmx_pip_get_port_status() 391 stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num)); in cvmx_pip_get_port_status() 392 stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num)); in cvmx_pip_get_port_status() 393 stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num)); in cvmx_pip_get_port_status() 394 stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num)); in cvmx_pip_get_port_status() 395 stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num)); in cvmx_pip_get_port_status() 396 stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num)); in cvmx_pip_get_port_status() 397 stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num)); in cvmx_pip_get_port_status() 398 stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num)); in cvmx_pip_get_port_status() [all …]
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D | cvmx-mdio.h | 273 smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id)); in __cvmx_mdio_set_clause45_mode() 284 smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id)); in __cvmx_mdio_set_clause22_mode() 317 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id)); in cvmx_mdio_read() 360 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); in cvmx_mdio_write() 406 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); in cvmx_mdio_45_read() 423 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id)); in cvmx_mdio_45_read() 481 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); in cvmx_mdio_45_write() 498 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); in cvmx_mdio_45_write()
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D | cvmx-fpa.h | 146 status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); in cvmx_fpa_enable() 161 cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull); in cvmx_fpa_enable() 186 cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool))); in cvmx_fpa_alloc()
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D | cvmx.h | 284 static inline uint64_t cvmx_read_csr(uint64_t csr_addr) in cvmx_read_csr() function 423 c.u64 = cvmx_read_csr(address); \ 442 uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff; in cvmx_octeon_num_cores()
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D | cvmx-pko.h | 589 pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0); in cvmx_pko_get_port_status() 596 pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1); in cvmx_pko_get_port_status() 607 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); in cvmx_pko_get_port_status() 613 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); in cvmx_pko_get_port_status()
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/arch/mips/pci/ |
D | pcie-octeon.c | 181 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port)); in cvmx_pcie_cfgx_read() 188 pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port)); in cvmx_pcie_cfgx_read() 438 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2); in __cvmx_pcie_rc_initialize_config_space() 458 prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port)); in __cvmx_pcie_rc_initialize_config_space() 465 sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port)); in __cvmx_pcie_rc_initialize_config_space() 596 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); in __cvmx_pcie_rc_initialize_link_gen1() 624 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); in __cvmx_pcie_rc_initialize_link_gen1() 647 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM)); in __cvmx_pcie_rc_initialize_link_gen1() 714 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); in __cvmx_pcie_rc_initialize_gen1() 725 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); in __cvmx_pcie_rc_initialize_gen1() [all …]
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D | msi-octeon.c | 276 en = cvmx_read_csr(mis_ena_reg[irq_index]); in octeon_irq_msi_enable_pcie() 279 cvmx_read_csr(mis_ena_reg[irq_index]); in octeon_irq_msi_enable_pcie() 292 en = cvmx_read_csr(mis_ena_reg[irq_index]); in octeon_irq_msi_disable_pcie() 295 cvmx_read_csr(mis_ena_reg[irq_index]); in octeon_irq_msi_disable_pcie() 352 u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \
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/arch/mips/cavium-octeon/ |
D | csrc-octeon.c | 43 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); in octeon_setup_delays() 50 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); in octeon_setup_delays() 80 u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT); in octeon_init_cvmcount()
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D | octeon-platform.c | 134 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); in octeon2_usb_clocks_start() 203 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); in octeon2_usb_clocks_start() 227 uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0)); in octeon2_usb_clocks_start() 275 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0)); in octeon2_usb_clocks_start() 324 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0)); in octeon_ehci_hw_start() 389 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); in octeon_ohci_hw_start() 799 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); in octeon_prune_device_tree() 822 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); in octeon_prune_device_tree() 888 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); in octeon_prune_device_tree()
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