/arch/mips/cavium-octeon/executive/ |
D | cvmx-helper-rgmii.c | 114 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); in cvmx_helper_rgmii_internal_loopback() 115 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); in cvmx_helper_rgmii_internal_loopback() 116 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); in cvmx_helper_rgmii_internal_loopback() 117 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); in cvmx_helper_rgmii_internal_loopback() 119 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback() 121 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback() 123 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback() 125 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); in cvmx_helper_rgmii_internal_loopback() 143 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12); in __cvmx_helper_errata_asx_pass1() 145 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11); in __cvmx_helper_errata_asx_pass1() [all …]
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D | cvmx-helper-xaui.c | 81 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); in __cvmx_helper_xaui_probe() 103 cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); in __cvmx_helper_xaui_probe() 131 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); in __cvmx_helper_xaui_enable() 139 cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); in __cvmx_helper_xaui_enable() 143 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); in __cvmx_helper_xaui_enable() 145 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); in __cvmx_helper_xaui_enable() 147 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); in __cvmx_helper_xaui_enable() 156 cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64); in __cvmx_helper_xaui_enable() 167 cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64); in __cvmx_helper_xaui_enable() 188 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); in __cvmx_helper_xaui_enable() [all …]
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D | cvmx-spi.c | 208 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); in cvmx_spi_reset_cb() 210 cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); in cvmx_spi_reset_cb() 213 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0); in cvmx_spi_reset_cb() 214 cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0); in cvmx_spi_reset_cb() 217 cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); in cvmx_spi_reset_cb() 238 cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), in cvmx_spi_reset_cb() 243 cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), in cvmx_spi_reset_cb() 248 cvmx_write_csr(CVMX_SPXX_INT_REG(interface), in cvmx_spi_reset_cb() 250 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); in cvmx_spi_reset_cb() 251 cvmx_write_csr(CVMX_STXX_INT_REG(interface), in cvmx_spi_reset_cb() [all …]
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D | cvmx-helper-sgmii.c | 66 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); in __cvmx_helper_sgmii_hardware_init_one_time() 86 cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time() 107 cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time() 122 cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG in __cvmx_helper_sgmii_hardware_init_one_time() 157 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_link() 176 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_link() 218 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); in __cvmx_helper_sgmii_hardware_init_link_speed() 261 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); in __cvmx_helper_sgmii_hardware_init_link_speed() 262 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); in __cvmx_helper_sgmii_hardware_init_link_speed() 269 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); in __cvmx_helper_sgmii_hardware_init_link_speed() [all …]
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D | cvmx-pko.c | 107 cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64); in __cvmx_pko_iport_config() 133 cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64); in __cvmx_pko_port_map_o68() 154 cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64); in __cvmx_pko_port_map_o68() 198 cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64); in cvmx_pko_initialize_global() 220 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); in cvmx_pko_initialize_global() 222 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); in cvmx_pko_initialize_global() 225 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); in cvmx_pko_initialize_global() 227 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); in cvmx_pko_initialize_global() 266 cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64); in cvmx_pko_enable() 277 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); in cvmx_pko_disable() [all …]
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D | cvmx-interrupt-decodes.c | 54 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), in __cvmx_interrupt_gmxx_rxx_int_en_enable() 227 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64); in __cvmx_interrupt_gmxx_rxx_int_en_enable() 235 cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), in __cvmx_interrupt_pcsx_intx_en_reg_enable() 268 cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64); in __cvmx_interrupt_pcsx_intx_en_reg_enable() 276 cvmx_write_csr(CVMX_PCSXX_INT_REG(index), in __cvmx_interrupt_pcsxx_int_en_reg_enable() 297 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64); in __cvmx_interrupt_pcsxx_int_en_reg_enable() 306 cvmx_write_csr(CVMX_SPXX_INT_REG(index), in __cvmx_interrupt_spxx_int_msk_enable() 337 cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64); in __cvmx_interrupt_spxx_int_msk_enable() 345 cvmx_write_csr(CVMX_STXX_INT_REG(index), in __cvmx_interrupt_stxx_int_msk_enable() 370 cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64); in __cvmx_interrupt_stxx_int_msk_enable()
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D | cvmx-helper-util.c | 193 cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64); in cvmx_helper_setup_red_queue() 202 cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64); in cvmx_helper_setup_red_queue() 233 cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), in cvmx_helper_setup_red() 244 cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64); in cvmx_helper_setup_red() 250 cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64); in cvmx_helper_setup_red() 277 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64); in __cvmx_helper_setup_gmx() 297 cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64); in __cvmx_helper_setup_gmx() 328 cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); in __cvmx_helper_setup_gmx() 359 cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), in __cvmx_helper_setup_gmx()
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D | cvmx-helper-board.c | 687 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0); in __cvmx_helper_board_hardware_enable() 688 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); in __cvmx_helper_board_hardware_enable() 694 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), in __cvmx_helper_board_hardware_enable() 696 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), in __cvmx_helper_board_hardware_enable() 734 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX in __cvmx_helper_board_hardware_enable() 736 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX in __cvmx_helper_board_hardware_enable() 743 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0); in __cvmx_helper_board_hardware_enable() 744 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10); in __cvmx_helper_board_hardware_enable() 745 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); in __cvmx_helper_board_hardware_enable() 746 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10); in __cvmx_helper_board_hardware_enable() [all …]
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D | cvmx-helper.c | 660 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); in __cvmx_helper_global_setup_pko() 673 cvmx_write_csr(CVMX_PKO_REG_MIN_PKT, min_pkt.u64); in __cvmx_helper_global_setup_pko() 825 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0); in __cvmx_helper_errata_fix_ipd_ptr_alignment() 847 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), in __cvmx_helper_errata_fix_ipd_ptr_alignment() 905 cvmx_write_csr(CVMX_GMXX_PRTX_CFG in __cvmx_helper_errata_fix_ipd_ptr_alignment() 908 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), in __cvmx_helper_errata_fix_ipd_ptr_alignment() 910 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), in __cvmx_helper_errata_fix_ipd_ptr_alignment() 913 cvmx_write_csr(CVMX_GMXX_RXX_JABBER in __cvmx_helper_errata_fix_ipd_ptr_alignment() 916 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX in __cvmx_helper_errata_fix_ipd_ptr_alignment() 948 cvmx_write_csr(CVMX_GMXX_PRTX_CFG in __cvmx_helper_errata_fix_ipd_ptr_alignment() [all …]
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D | cvmx-helper-jtag.c | 69 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_init() 96 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_shift() 140 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_update()
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D | cvmx-l2c.c | 102 cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask); in cvmx_l2c_set_core_way_partition() 119 cvmx_write_csr(CVMX_L2C_SPAR0, in cvmx_l2c_set_core_way_partition() 124 cvmx_write_csr(CVMX_L2C_SPAR1, in cvmx_l2c_set_core_way_partition() 129 cvmx_write_csr(CVMX_L2C_SPAR2, in cvmx_l2c_set_core_way_partition() 134 cvmx_write_csr(CVMX_L2C_SPAR3, in cvmx_l2c_set_core_way_partition() 154 cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask); in cvmx_l2c_set_hw_way_partition() 156 cvmx_write_csr(CVMX_L2C_SPAR4, in cvmx_l2c_set_hw_way_partition() 201 cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64); in cvmx_l2c_config_perf() 228 cvmx_write_csr(CVMX_L2C_TADX_PRF(tad), in cvmx_l2c_config_perf() 361 cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64); in cvmx_l2c_lock_line() [all …]
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D | cvmx-helper-loop.c | 62 cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); in __cvmx_helper_loop_probe() 68 cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); in __cvmx_helper_loop_probe()
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D | cvmx-interrupt-rsl.c | 69 cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64); in __cvmx_interrupt_asxx_enable() 137 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); in __cvmx_interrupt_gmxx_enable()
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D | cvmx-helper-spi.c | 91 cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64); in __cvmx_helper_spi_probe() 120 cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64); in __cvmx_helper_spi_enable()
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/arch/mips/include/asm/octeon/ |
D | cvmx-ipd.h | 94 cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); in cvmx_ipd_config() 98 cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); in cvmx_ipd_config() 102 cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); in cvmx_ipd_config() 106 cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); in cvmx_ipd_config() 110 cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64); in cvmx_ipd_config() 114 cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); in cvmx_ipd_config() 119 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); in cvmx_ipd_config() 141 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); in cvmx_ipd_enable() 152 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); in cvmx_ipd_disable() 203 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, in cvmx_ipd_free_ptr() [all …]
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D | cvmx-mdio.h | 276 cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64); in __cvmx_mdio_set_clause45_mode() 286 cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64); in __cvmx_mdio_set_clause22_mode() 313 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); in cvmx_mdio_read() 350 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); in cvmx_mdio_write() 356 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); in cvmx_mdio_write() 396 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); in cvmx_mdio_45_read() 402 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); in cvmx_mdio_45_read() 419 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); in cvmx_mdio_45_read() 471 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); in cvmx_mdio_45_write() 477 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); in cvmx_mdio_45_write() [all …]
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D | cvmx-pip.h | 296 cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64); in cvmx_pip_config_port() 297 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64); in cvmx_pip_config_port() 327 cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64); 343 cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64); in cvmx_pip_config_vlan_qos() 357 cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64); in cvmx_pip_config_diffserv_qos() 387 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); in cvmx_pip_get_port_status() 470 cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64); in cvmx_pip_config_crc() 474 cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64); in cvmx_pip_config_crc() 493 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); in cvmx_pip_tag_mask_clear() 519 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); in cvmx_pip_tag_mask_set()
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D | cvmx-pko.h | 587 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); in cvmx_pko_get_port_status() 593 cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64); in cvmx_pko_get_port_status() 600 cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64); in cvmx_pko_get_port_status() 606 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); in cvmx_pko_get_port_status() 612 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); in cvmx_pko_get_port_status()
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D | cvmx-fpa.h | 163 cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull, in cvmx_fpa_enable() 174 cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64); in cvmx_fpa_enable()
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/arch/mips/cavium-octeon/ |
D | octeon-irq.c | 275 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_enable() 284 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_enable() 307 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); in octeon_irq_ciu_enable_local() 316 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); in octeon_irq_ciu_enable_local() 339 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); in octeon_irq_ciu_disable_local() 348 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); in octeon_irq_ciu_disable_local() 379 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_disable_all() 381 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_disable_all() 412 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_enable_all() 414 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_enable_all() [all …]
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D | setup.c | 191 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); in octeon_generic_shutdown() 193 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); in octeon_generic_shutdown() 261 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); in octeon_crash_smp_send_stop() 423 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); in octeon_restart() 425 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); in octeon_restart() 431 cvmx_write_csr(CVMX_RST_SOFT_RST, 1); in octeon_restart() 433 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); in octeon_restart() 450 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); in octeon_kill_core() 467 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); in octeon_halt() 468 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); in octeon_halt() [all …]
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D | smp.c | 42 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action); in mailbox_interrupt() 67 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); in octeon_send_ipi_single() 205 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); in octeon_prepare_cpus() 286 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); in octeon_cpu_die() 287 cvmx_write_csr(CVMX_CIU_PP_RST, 0); in octeon_cpu_die() 336 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); in octeon_update_boot_vector() 337 cvmx_write_csr(CVMX_CIU_PP_RST, 0); in octeon_update_boot_vector() 346 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); in octeon_update_boot_vector()
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D | octeon-platform.c | 131 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); in octeon2_usb_clocks_start() 150 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start() 169 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start() 201 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start() 205 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start() 208 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start() 218 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start() 229 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64); in octeon2_usb_clocks_start() 236 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64); in octeon2_usb_clocks_start() 247 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start() [all …]
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/arch/mips/pci/ |
D | pcie-octeon.c | 180 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64); in cvmx_pcie_cfgx_read() 187 cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64); in cvmx_pcie_cfgx_read() 209 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64); in cvmx_pcie_cfgx_write() 215 cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64); in cvmx_pcie_cfgx_write() 448 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); in __cvmx_pcie_rc_initialize_config_space() 463 cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64); in __cvmx_pcie_rc_initialize_config_space() 467 cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64); in __cvmx_pcie_rc_initialize_config_space() 620 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64); in __cvmx_pcie_rc_initialize_link_gen1() 626 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64); in __cvmx_pcie_rc_initialize_link_gen1() 647 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM)); in __cvmx_pcie_rc_initialize_link_gen1() [all …]
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D | pci-octeon.c | 372 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1); in octeon_pci_initialize() 380 cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64); in octeon_pci_initialize() 384 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4); in octeon_pci_initialize() 501 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64); in octeon_pci_initialize() 609 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64); in octeon_pci_setup() 703 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); in octeon_pci_setup()
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