Searched refs:deadlock (Results 1 – 4 of 4) sorted by relevance
174 int active, max_active, deadlock, flush_opt = sn2_flush_opt; in sn2_global_tlb_purge() local271 deadlock = 0; in sn2_global_tlb_purge()286 if ((deadlock = wait_piowc())) { in sn2_global_tlb_purge()313 if (flush_opt == 1 && deadlock) { in sn2_global_tlb_purge()
256 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…266 system can deadlock.341 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"347 Affected Cortex-A57 parts might deadlock when exclusive load/store703 with SWP emulation enabled, leading to deadlock of the user710 perform SWP operations to uncached memory to deadlock.
1082 bool "ARM errata: Processor deadlock when a false hazard is created"1090 hazard might then cause a processor deadlock. The workaround enables1233 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"1239 to deadlock. This workaround puts DSB before executing ISB if
704 with SWP emulation enabled, leading to deadlock of the user711 perform SWP operations to uncached memory to deadlock.