Searched refs:dev_base (Results 1 – 5 of 5) sorted by relevance
277 int dev_base, dev_limit; in early_gart_iommu_check() local280 dev_base = amd_nb_bus_dev_ranges[i].dev_base; in early_gart_iommu_check()283 for (slot = dev_base; slot < dev_limit; slot++) { in early_gart_iommu_check()333 int dev_base, dev_limit; in early_gart_iommu_check() local336 dev_base = amd_nb_bus_dev_ranges[i].dev_base; in early_gart_iommu_check()339 for (slot = dev_base; slot < dev_limit; slot++) { in early_gart_iommu_check()377 int dev_base, dev_limit; in gart_iommu_hole_init() local381 dev_base = amd_nb_bus_dev_ranges[i].dev_base; in gart_iommu_hole_init()384 for (slot = dev_base; slot < dev_limit; slot++) { in gart_iommu_hole_init()485 int bus, dev_base, dev_limit; in gart_iommu_hole_init() local[all …]
42 u32 dev_base = base | PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12); in pci_exp_set_dev_base() local44 if (dev_base != mmcfg_last_accessed_device || in pci_exp_set_dev_base()46 mmcfg_last_accessed_device = dev_base; in pci_exp_set_dev_base()48 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base); in pci_exp_set_dev_base()
366 u8 slot = amd_nb_bus_dev_ranges[i].dev_base; in pci_enable_pci_io_ecs()
9 u8 dev_base; member
625 u32 dev_base; member675 u32 dev_base = bus->number << 24 | devfn << 16; in mpc83xx_pcie_remap_cfg() local688 if (pcie->dev_base == dev_base) in mpc83xx_pcie_remap_cfg()691 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); in mpc83xx_pcie_remap_cfg()693 pcie->dev_base = dev_base; in mpc83xx_pcie_remap_cfg()